This is the course project for the Computer Organization Principles course of the 17th class at Nanjing Agricultural University. It implements the functionality of an 8-bit CPU based on a pipelined structure and the TEC-5 instruction set, following the structure diagram of the MIPS pipeline. The project was mainly implemented using the hardware simulation platform PROTEUS, achieving the functionality of the TEC-5 model machine. The final system developed in this project consists of an arithmetic unit, controller, clock pulse signal generator, dual-port general-purpose register file, and instruction data memory. It can execute instructions in both manual and automatic modes. In the manual mode, instructions can be executed after manually inputting data, while in the automatic mode, the system can automatically execute seven instructions such as ADD and SUB in a pipelined manner. The project includes bypass units and control logic.
这是南京农业大学17级计算机组成原理课程设计，仿MIPS流水线结构图实现了基于流水线结构和TEC-5指令的8位CPU的功能，基本上完成了在硬件仿真平台PROTEUS上实现TEC-5模型机的功能。系统由运算器、控制器、时钟脉冲信号发生器、双端口通用寄存器堆和指令数据存储器等组成，能够在手动模式和自动模式下执行，手动输入数据之后可切换到自动模式执行指令，在自动模式下能以流水线的方式自动执行ADD，SUB等7条指令。项目包含旁路单元与控制逻辑.