MIPS_Single_Cycle_architecture

A sample architecture of a MIPS single cycle processor

Name		Name	Last commit message	Last commit date
Latest commit History 13 Commits
README.md		README.md
adder32.v		adder32.v
data-memory.v		data-memory.v
extend.v		extend.v
instruction-mem.v		instruction-mem.v
mips-alu.v		mips-alu.v
mips-control.v		mips-control.v
mips-decode.v		mips-decode.v
mips-tb.v		mips-tb.v
mips.v		mips.v
mux32-2x1.v		mux32-2x1.v
mux5-2x1.v		mux5-2x1.v
pc-reg.v		pc-reg.v

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