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rockchip: fixes rk3588 usb3 init issue
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39 changes: 39 additions & 0 deletions
39
target/linux/rockchip/patches-6.1/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,39 @@ | ||
| --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi | ||
| +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi | ||
| @@ -225,6 +225,7 @@ | ||
| assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; | ||
| assigned-clock-rates = <100000000>; | ||
| resets = <&cru SRST_PIPEPHY0>; | ||
| + reset-names = "phy"; | ||
| rockchip,pipe-grf = <&pipegrf>; | ||
| rockchip,pipe-phy-grf = <&pipe_phy_grf0>; | ||
| #phy-cells = <1>; | ||
| --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi | ||
| +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi | ||
| @@ -1686,6 +1686,7 @@ | ||
| assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; | ||
| assigned-clock-rates = <100000000>; | ||
| resets = <&cru SRST_PIPEPHY1>; | ||
| + reset-names = "phy"; | ||
| rockchip,pipe-grf = <&pipegrf>; | ||
| rockchip,pipe-phy-grf = <&pipe_phy_grf1>; | ||
| #phy-cells = <1>; | ||
| @@ -1702,6 +1703,7 @@ | ||
| assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; | ||
| assigned-clock-rates = <100000000>; | ||
| resets = <&cru SRST_PIPEPHY2>; | ||
| + reset-names = "phy"; | ||
| rockchip,pipe-grf = <&pipegrf>; | ||
| rockchip,pipe-phy-grf = <&pipe_phy_grf2>; | ||
| #phy-cells = <1>; | ||
| --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | ||
| +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | ||
| @@ -299,7 +299,7 @@ static int rockchip_combphy_parse_dt(str | ||
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||
| priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); | ||
|
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||
| - priv->phy_rst = devm_reset_control_array_get_exclusive(dev); | ||
| + priv->phy_rst = devm_reset_control_get(dev, "phy"); | ||
| if (IS_ERR(priv->phy_rst)) | ||
| return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); | ||
|
|
39 changes: 39 additions & 0 deletions
39
target/linux/rockchip/patches-6.6/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,39 @@ | ||
| --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi | ||
| +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi | ||
| @@ -225,6 +225,7 @@ | ||
| assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; | ||
| assigned-clock-rates = <100000000>; | ||
| resets = <&cru SRST_PIPEPHY0>; | ||
| + reset-names = "phy"; | ||
| rockchip,pipe-grf = <&pipegrf>; | ||
| rockchip,pipe-phy-grf = <&pipe_phy_grf0>; | ||
| #phy-cells = <1>; | ||
| --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi | ||
| +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi | ||
| @@ -1719,6 +1719,7 @@ | ||
| assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; | ||
| assigned-clock-rates = <100000000>; | ||
| resets = <&cru SRST_PIPEPHY1>; | ||
| + reset-names = "phy"; | ||
| rockchip,pipe-grf = <&pipegrf>; | ||
| rockchip,pipe-phy-grf = <&pipe_phy_grf1>; | ||
| #phy-cells = <1>; | ||
| @@ -1735,6 +1736,7 @@ | ||
| assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; | ||
| assigned-clock-rates = <100000000>; | ||
| resets = <&cru SRST_PIPEPHY2>; | ||
| + reset-names = "phy"; | ||
| rockchip,pipe-grf = <&pipegrf>; | ||
| rockchip,pipe-phy-grf = <&pipe_phy_grf2>; | ||
| #phy-cells = <1>; | ||
| --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | ||
| +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | ||
| @@ -324,7 +324,7 @@ static int rockchip_combphy_parse_dt(str | ||
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| priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); | ||
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||
| - priv->phy_rst = devm_reset_control_array_get_exclusive(dev); | ||
| + priv->phy_rst = devm_reset_control_get(dev, "phy"); | ||
| if (IS_ERR(priv->phy_rst)) | ||
| return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); | ||
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|