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bios: Make sure PVH still works with "rom" feature
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Without this change, QEMU/CloudHV will attempt to load the ROM into the
memory region below 4GiB. But something (i.e. SeaBIOS) is already there.

We just pick an arbitrary address. It doesn't actually matter where it
gets loaded, as the ROM code isn't used when doing PVH boot.

Signed-off-by: Joe Richey <[email protected]>
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josephlr committed Sep 10, 2020
1 parent ae54aed commit 8961efc
Showing 1 changed file with 7 additions and 6 deletions.
13 changes: 7 additions & 6 deletions layout.ld
Original file line number Diff line number Diff line change
@@ -1,15 +1,17 @@
ENTRY(rust64_start) /* This firmware doesn't use the ELF entrypoint */

/* Loaders like to put stuff in low memory (< 1M), so we don't use it. */
ram_min = 1M;
/* ram32.s only maps the first 2 MiB, which must include our whole program. */
ram_max = 2M;

PHDRS
{
ram PT_LOAD FILEHDR PHDRS ;
note PT_NOTE ;
rom PT_LOAD ;
rom PT_LOAD AT(ram_max) ;
}

/* Loaders like to put stuff in low memory (< 1M), so we don't use it. */
ram_min = 1M;

SECTIONS
{
/* Mapping the program headers and note into RAM makes the file smaller. */
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/* Our stack grows down and is page-aligned. TODO: Add stack guard pages. */
.stack (NOLOAD) : ALIGN(4K) { . += 64K; }
stack_start = .;
/* ram32.s only maps the first 2 MiB, and that must include the stack. */
ASSERT((. <= 2M), "Stack overflows initial identity-mapped memory region")
ASSERT((. <= ram_max), "Stack overflows initial identity-mapped region")

/* This is correct because all of the code sections have alignment 16. */
rom_size = ALIGN(SIZEOF(.gdt32), 16) + ALIGN(SIZEOF(.rom32), 16)
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