pci: Handle overflow on 32-bit PCI BAR size calculation

The firmware panics if the calculated 32-bit BAR size overflows on debug build. Signed-off-by: Akira Moroo <[email protected]>
cloud-hypervisor · Mar 21, 2023 · 573f46c · 573f46c
1 parent 37aaff9
commit 573f46c
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/src/pci.rs b/src/pci.rs
@@ -302,7 +302,9 @@ impl PciDevice {
                         self.bars[current_bar].address = u64::from(bar & 0xffff_fff0);
 
                         self.write_u32(current_bar_offset, 0xffff_ffff);
-                        let size = !(self.read_u32(current_bar_offset) & 0xffff_fff0) + 1;
+                        let size = (!(self.read_u32(current_bar_offset) & 0xffff_fff0))
+                            .checked_add(1)
+                            .unwrap_or(0);
                         self.bars[current_bar].size = u64::from(size);
                         self.write_u32(current_bar_offset, bar);
                     }