Use Clash length of type instead of VHDL length inference. Fix #373 #376
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christiaanb
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Oct 10, 2018
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Referencing `'length` and `'range' might cause problems when dealing with 'empty' vectors, such as a vector of units. Thus, this commit removes references to it, except in cases where it is used on ~RESULT, as we assume that a function result is not empty (as it should have been removed by Clash). This commit only affects VHDL, as we do not use these constructs for Verilog.
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I've removed a number of other references to |
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@martijnbastiaan the approved is a yes to your question, the |
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Perfect, thanks, I'll merge it soon. |
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Please see this issue.
While all test cases perfectly pass, I wonder if this patch is actually correct:
'rangeconstructs with just literals?~IF ~VIVADOconstruct still valid after this patch?