Change Signal.fromList's tail from errorX to error

By making the undefined tail of a signal created with fromList
into an error instead of errorX, this makes it clear when
you're trying use a signal without enough input data.

A problem with the errorX was that in certain circumstances it can be
turned into a signal full of XException. That can turn into a signal
full of undefined BitVectors.
And when that is used as the basis for the expected values
of a outputVerifierBitVector you end up with a testbench that reports
everything is fine for some (possibly big) part of the test.

Also add HasCallStack to Signal.fromList to help with tracing this error.

clash-prelude/src/Clash/Explicit/Prelude.hs

@@ -263,7 +263,7 @@ window clk rst en x = res
 -- @
 --
 -- >>> simulateB (windowD3 systemClockGen resetGen enableGen) [1::Int,1,2,3,4] :: [Vec 3 Int]
--- [0 :> 0 :> 0 :> Nil,0 :> 0 :> 0 :> Nil,1 :> 0 :> 0 :> Nil,2 :> 1 :> 0 :> Nil,3 :> 2 :> 1 :> Nil,4 :> 3 :> 2 :> Nil,...
+-- [0 :> 0 :> 0 :> Nil,0 :> 0 :> 0 :> Nil,1 :> 0 :> 0 :> Nil,2 :> 1 :> 0 :> Nil,3 :> 2 :> 1 :> Nil,4 :> 3 :> 2 :> Nil...
 -- ...
 windowD
   :: ( KnownNat n

clash-prelude/src/Clash/Prelude.hs

@@ -244,7 +244,7 @@ functions a type class called 'Clash.Class.Parity.Parity' is available at
 -- > window4 = window
 --
 -- >>> simulateB @System window4 [1::Int,2,3,4,5] :: [Vec 4 Int]
--- [1 :> 0 :> 0 :> 0 :> Nil,2 :> 1 :> 0 :> 0 :> Nil,3 :> 2 :> 1 :> 0 :> Nil,4 :> 3 :> 2 :> 1 :> Nil,5 :> 4 :> 3 :> 2 :> Nil,...
+-- [1 :> 0 :> 0 :> 0 :> Nil,2 :> 1 :> 0 :> 0 :> Nil,3 :> 2 :> 1 :> 0 :> Nil,4 :> 3 :> 2 :> 1 :> Nil,5 :> 4 :> 3 :> 2 :> Nil...
 -- ...
 window
   :: ( HiddenClockResetEnable dom
@@ -267,7 +267,7 @@ window = hideClockResetEnable E.window
 -- > windowD3 = windowD
 --
 -- >>> simulateB @System windowD3 [1::Int,2,3,4] :: [Vec 3 Int]
--- [0 :> 0 :> 0 :> Nil,1 :> 0 :> 0 :> Nil,2 :> 1 :> 0 :> Nil,3 :> 2 :> 1 :> Nil,4 :> 3 :> 2 :> Nil,...
+-- [0 :> 0 :> 0 :> Nil,1 :> 0 :> 0 :> Nil,2 :> 1 :> 0 :> Nil,3 :> 2 :> 1 :> Nil,4 :> 3 :> 2 :> Nil...
 -- ...
 windowD
   :: ( HiddenClockResetEnable dom

clash-prelude/src/Clash/Prelude/Moore.hs

@@ -61,7 +61,7 @@ let macT s (x,y) = x * y + s
 -- @
 --
 -- >>> simulate @System mac [(0,0),(1,1),(2,2),(3,3),(4,4)]
--- [0,0,1,5,14,30,...
+-- [0,0,1,5,14,30...
 -- ...
 --
 -- Synchronous sequential functions can be composed just like their

clash-prelude/src/Clash/Signal/Internal.hs

@@ -204,7 +204,7 @@ import Clash.NamedTypes
 import Clash.Promoted.Nat         (SNat (..), snatToNum, snatToNatural)
 import Clash.Promoted.Symbol      (SSymbol (..), ssymbolToString)
 import Clash.XException
-  (NFDataX(..), errorX, isX, deepseqX, defaultSeqX, seqX)
+  (NFDataX(..), isX, deepseqX, defaultSeqX, seqX)
 
 {- $setup
 >>> :set -XDataKinds
@@ -1689,8 +1689,8 @@ sampleN n = take n . sample
 -- [1,2]
 --
 -- __NB__: This function is not synthesizable
-fromList :: NFDataX a => [a] -> Signal dom a
-fromList = Prelude.foldr (\a b -> deepseqX a (a :- b)) (errorX "finite list")
+fromList :: (HasCallStack,NFDataX a) => [a] -> Signal dom a
+fromList = Prelude.foldr (\a b -> deepseqX a (a :- b)) (error "finite list")
 
 -- * Simulation functions (not synthesizable)