Add index to assingnment pattern in SV

Without them, the following SV tests fail on QuestaSim Intel Starter Edition 2023.1: * T1524 * Transpose * VMerge
clash-lang · Nov 3, 2023 · 3b4c7f9 · 3b4c7f9
1 parent a0be49f
commit 3b4c7f9
Show file tree

Hide file tree

Showing 2 changed files with 3 additions and 2 deletions.
diff --git a/changelog/2023-10-31T11_39_43+01_00_sv_compat b/changelog/2023-10-31T11_39_43+01_00_sv_compat
@@ -0,0 +1 @@
+FIXED: SystemVerilog backend: Assignment patterns for unpacked arrays now have an index for every element; improves QuestaSim compatibility.
diff --git a/clash-lib/src/Clash/Backend/SystemVerilog.hs b/clash-lib/src/Clash/Backend/SystemVerilog.hs
@@ -1147,10 +1147,10 @@ expr_ b (DataCon _ (DC (Void {}, -1)) [e]) =  expr_ b e
 
 expr_ _ (DataCon ty@(Vector 0 _) _ _) = verilogTypeErrValue ty
 
-expr_ _ (DataCon (Vector 1 elTy) _ [e]) = "'" <> braces (toSLV elTy e)
+expr_ _ (DataCon (Vector 1 elTy) _ [e]) = "'" <> braces (int 0 <> colon <+> toSLV elTy e)
 
 expr_ _ e@(DataCon ty@(Vector _ elTy) _ [e1,e2]) = case vectorChain e of
-  Just es -> "'" <> listBraces (mapM (toSLV elTy) es)
+  Just es -> "'" <> listBraces (zipWithM (\i e3 -> int i <> colon <+> toSLV elTy e3) [0..] es)
   Nothing -> verilogTypeMark ty <> "_cons" <> parens (expr_ False e1 <> comma <+> expr_ False e2)
 
 expr_ _ (DataCon (MemBlob n m) _ [n0, m0, _, runs, _, ends])
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		FIXED: SystemVerilog backend: Assignment patterns for unpacked arrays now have an index for every element; improves QuestaSim compatibility.