Fix Werror: empty argument list

src/main/scala/interrupts/Nodes.scala

@@ -21,7 +21,7 @@ object IntImp extends SimpleNodeImp[IntSourcePortParameters, IntSinkPortParamete
 
 trait IntFormatNode extends BaseNode
 {
-  override def formatNode() = "Interrupt Node\n"
+  override def formatNode = "Interrupt Node\n"
 }
 
 case class IntSourceNode(portParams: Seq[IntSourcePortParameters])(implicit valName: ValName) extends SourceNode(IntImp)(portParams) with IntFormatNode

src/main/scala/jtag/JtagStateMachine.scala

@@ -70,7 +70,7 @@ object JtagState {
 class JtagStateMachine(implicit val p: Parameters) extends Module() {
   class StateMachineIO extends Bundle {
     val tms = Input(Bool())
-    val currState = Output(JtagState.State.chiselType)
+    val currState = Output(JtagState.State.chiselType())
   }
   val io = IO(new StateMachineIO)
 

src/main/scala/jtag/JtagTap.scala

@@ -72,7 +72,7 @@ class JtagTapController(irLength: Int, initialInstruction: BigInt)(implicit val
   // JTAG state machine
   //
 
-  val currState = Wire(JtagState.State.chiselType)
+  val currState = Wire(JtagState.State.chiselType())
 
   // At this point, the TRSTn should already have been
   // combined with any POR, and it should also be

src/main/scala/subsystem/BaseSubsystem.scala

@@ -31,7 +31,7 @@ abstract class BareSubsystemModuleImp[+L <: BareSubsystem](_outer: L) extends La
   ElaborationArtefacts.add("graphml", outer.graphML)
   ElaborationArtefacts.add("dts", outer.dts)
   ElaborationArtefacts.add("json", outer.json)
-  ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader)
+  ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader())
   println(outer.dts)
 }
 

src/main/scala/tilelink/Arbiter.scala

@@ -91,7 +91,7 @@ object TLArbiter
 
       // Who wants access to the sink?
       val earlyValids = sourcesIn.map(_.earlyValid)
-      val validQuals  = sourcesIn.map(_.validQual)
+      val validQuals  = sourcesIn.map(_.validQual())
       // Arbitrate amongst the requests
       val readys = VecInit(policy(earlyValids.size, Cat(earlyValids.reverse), latch).asBools)
       // Which request wins arbitration?

src/main/scala/tilelink/AtomicAutomata.scala

@@ -46,7 +46,7 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
 
       // Managers that need help with atomics must necessarily have this node as the root of a tree in the node graph.
       // (But they must also ensure no sideband operations can get between the read and write.)
-      val violations = managersNeedingHelp.flatMap(_.findTreeViolation).map { node => (node.name, node.inputs.map(_._1.name)) }
+      val violations = managersNeedingHelp.flatMap(_.findTreeViolation()).map { node => (node.name, node.inputs.map(_._1.name)) }
       require(violations.isEmpty,
         s"AtomicAutomata can only help nodes for which it is at the root of a diplomatic node tree," +
         "but the following violations were found:\n" +

src/main/scala/tilelink/Buffer.scala

@@ -112,7 +112,7 @@ class TLBufferAndNotCancel(
   lazy val module = new Impl
   class Impl extends LazyModuleImp(this) {
     (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
-      out.a <> a(in.a.asDecoupled)
+      out.a <> a(in.a.asDecoupled())
       in .d <> d(out.d)
 
       if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {

src/main/scala/unittest/UnitTest.scala

@@ -23,7 +23,7 @@ trait UnitTestLegacyModule extends HasUnitTestIO {
 
 trait UnitTestModule extends Module with HasUnitTestIO {
   val io = IO(new Bundle with UnitTestIO)
-  ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader)
+  ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader())
 }
 
 abstract class UnitTest(val timeout: Int = 4096) extends Module with UnitTestLegacyModule {

src/main/scala/util/ReadyValidCancel.scala

@@ -157,7 +157,7 @@ class ReadyValidCancelRRArbiter[T <: Data](gen: T, n: Int, rr: Boolean) extends
     when (io.out.earlyValid) {
       assert(selectEnc_q < n.U, "arbiter round-robin select out of range")
     }
-    when (io.in(selectEnc_q).mightFire && io.in.map(i => i.earlyValid && !i.ready).orR) {
+    when (io.in(selectEnc_q).mightFire() && io.in.map(i => i.earlyValid && !i.ready).orR) {
       assert(selectEnc_in =/= selectEnc_q, "arbiter round-robin select did not advance")
     }
   }

src/main/scala/util/package.scala

@@ -68,7 +68,7 @@ package object util {
     def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
     def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
     def >> (n: Int): Seq[Bool] = x drop n
-    def unary_~(): Seq[Bool] = x.map(!_)
+    def unary_~ : Seq[Bool] = x.map(!_)
     def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
     def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
     def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)