fix: add chiselTypeOf when inst Wire(in.d)

chipsalliance · Mar 1, 2023 · e645d94 · e645d94
1 parent 1ff0db3
commit e645d94
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/main/scala/devices/tilelink/Error.scala b/src/main/scala/devices/tilelink/Error.scala
@@ -22,7 +22,7 @@ class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)
     val (in, edge) = node.in(0)
     val a = if (buffer) {Queue(in.a, 1)} else in.a
 
-    val da = Wire(in.d)
+    val da = Wire(chiselTypeOf(in.d))
     val idle = RegInit(true.B)
 
     val a_last = edge.last(a)
@@ -43,7 +43,7 @@ class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)
 
     if (params.acquire) {
       val c = if (buffer) {Queue(in.c, 1)} else in.c
-      val dc = Wire(in.d)
+      val dc = Wire(chiselTypeOf(in.d))
 
       val c_last = edge.last(c)
       val dc_last = edge.last(dc)