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remove vMemDataBits check
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sequencer committed Nov 23, 2023
1 parent 6b67317 commit df66c19
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1 change: 0 additions & 1 deletion src/main/scala/tile/Core.scala
Original file line number Diff line number Diff line change
Expand Up @@ -113,7 +113,6 @@ trait HasCoreParameters extends HasTileParameters {
if (usingVector) {
require(isPow2(vLen), s"vLen ($vLen) must be a power of 2")
require(eLen >= 32 && vLen % eLen == 0, s"eLen must divide vLen ($vLen) and be no less than 32")
require(vMemDataBits >= eLen && vLen % vMemDataBits == 0, s"vMemDataBits ($vMemDataBits) must divide vLen ($vLen) and be no less than eLen ($eLen)")
}

lazy val hartIdLen: Int = p(MaxHartIdBits)
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