Move clockCrossing types into prci

chipsalliance · Jun 6, 2024 · aea0064 · aea0064
1 parent f43041d
commit aea0064
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Showing 36 changed files with 60 additions and 64 deletions.
diff --git a/src/main/scala/amba/axi4/AsyncCrossing.scala b/src/main/scala/amba/axi4/AsyncCrossing.scala
@@ -9,7 +9,8 @@ import org.chipsalliance.cde.config.Parameters
 import org.chipsalliance.diplomacy.nodes.{NodeHandle}
 import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
 
-import freechips.rocketchip.diplomacy.{AddressSet, AsynchronousCrossing}
+import freechips.rocketchip.diplomacy.{AddressSet}
+import freechips.rocketchip.prci.{AsynchronousCrossing}
 import freechips.rocketchip.tilelink.{TLRAMModel, TLFuzzer, TLToAXI4}
 import freechips.rocketchip.subsystem.CrossingWrapper
 import freechips.rocketchip.util.{ToAsyncBundle, FromAsyncBundle, AsyncQueueParams, Pow2ClockDivider}

diff --git a/src/main/scala/amba/axi4/Credited.scala b/src/main/scala/amba/axi4/Credited.scala
@@ -8,7 +8,8 @@ import org.chipsalliance.cde.config.Parameters
 
 import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
 
-import freechips.rocketchip.diplomacy.{AddressSet, CreditedCrossing}
+import freechips.rocketchip.diplomacy.{AddressSet}
+import freechips.rocketchip.prci.{CreditedCrossing}
 import freechips.rocketchip.subsystem.CrossingWrapper
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._

diff --git a/src/main/scala/amba/axi4/CrossingHelper.scala b/src/main/scala/amba/axi4/CrossingHelper.scala
@@ -5,8 +5,7 @@ package freechips.rocketchip.amba.axi4
 import org.chipsalliance.cde.config.Parameters
 import org.chipsalliance.diplomacy.lazymodule.{LazyScope}
 
-import freechips.rocketchip.diplomacy.{CrossingType, ClockCrossingType, NoCrossing, AsynchronousCrossing, RationalCrossing, SynchronousCrossing, CreditedCrossing}
-import freechips.rocketchip.prci.{ResetCrossingType, NoResetCrossing, StretchedResetCrossing}
+import freechips.rocketchip.prci.{ResetCrossingType, NoResetCrossing, StretchedResetCrossing, CrossingType, ClockCrossingType, NoCrossing, AsynchronousCrossing, RationalCrossing, SynchronousCrossing, CreditedCrossing}
 
 trait AXI4OutwardCrossingHelper {
   type HelperCrossingType <: CrossingType

diff --git a/src/main/scala/amba/axi4/RegisterRouter.scala b/src/main/scala/amba/axi4/RegisterRouter.scala
@@ -10,7 +10,8 @@ import org.chipsalliance.cde.config.Parameters
 import org.chipsalliance.diplomacy.ValName
 import org.chipsalliance.diplomacy.nodes.{SinkNode}
 
-import freechips.rocketchip.diplomacy.{AddressSet, NoCrossing, TransferSizes}
+import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
+import freechips.rocketchip.prci.{NoCrossing}
 import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperInput, RegMapperParams, RegisterRouter}
 import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
 import freechips.rocketchip.util._

diff --git a/src/main/scala/amba/axi4/package.scala b/src/main/scala/amba/axi4/package.scala
@@ -5,8 +5,7 @@ package freechips.rocketchip.amba
 import org.chipsalliance.diplomacy.ValName
 import org.chipsalliance.diplomacy.nodes.{SimpleNodeHandle, OutwardNodeHandle, InwardNodeHandle}
 
-import freechips.rocketchip.diplomacy.HasClockDomainCrossing
-import freechips.rocketchip.prci.HasResetDomainCrossing
+import freechips.rocketchip.prci.{HasClockDomainCrossing, HasResetDomainCrossing}
 
 /**
   * Provide bundles, adapters and devices etc for AMBA AXI4 protocol.

diff --git a/src/main/scala/devices/tilelink/DevNull.scala b/src/main/scala/devices/tilelink/DevNull.scala
@@ -5,7 +5,8 @@ package freechips.rocketchip.devices.tilelink
 import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{AddressSet, HasClockDomainCrossing, RegionType, SimpleDevice, TransferSizes}
+import freechips.rocketchip.diplomacy.{AddressSet, RegionType, SimpleDevice, TransferSizes}
+import freechips.rocketchip.prci.{HasClockDomainCrossing}
 import freechips.rocketchip.tilelink.{TLManagerNode, TLSlaveParameters, TLSlavePortParameters}
 
 import freechips.rocketchip.tilelink.TLClockDomainCrossing

diff --git a/src/main/scala/diplomacy/package.scala b/src/main/scala/diplomacy/package.scala
@@ -47,8 +47,6 @@ package object diplomacy {
     def asProperty: Seq[ResourceValue] = Seq(ResourceReference(x.label))
   }
 
-  implicit def noCrossing(value: NoCrossing.type): ClockCrossingType = SynchronousCrossing(BufferParams.none)
-
   // TODO - Remove compatibility layer for deprecated diplomacy api once all local references are moved to standalone diplomacy lib.
   // package.scala
   @deprecated("Diplomacy has been split to a standalone library", "rocketchip 2.0.0")

diff --git a/src/main/scala/groundtest/Tile.scala b/src/main/scala/groundtest/Tile.scala
@@ -9,7 +9,8 @@ import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.bundlebridge._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{ClockCrossingType, SimpleDevice}
+import freechips.rocketchip.diplomacy.{SimpleDevice}
+import freechips.rocketchip.prci.{ClockCrossingType}
 import freechips.rocketchip.interrupts._
 import freechips.rocketchip.rocket.{BuildHellaCache, DCache, DCacheModule, ICacheParams, NonBlockingDCache, NonBlockingDCacheModule, RocketCoreParams}
 import freechips.rocketchip.tile._

diff --git a/src/main/scala/groundtest/TraceGen.scala b/src/main/scala/groundtest/TraceGen.scala
@@ -24,13 +24,12 @@ import chisel3.util._
 
 import org.chipsalliance.cde.config._
 
-import freechips.rocketchip.diplomacy.ClockCrossingType
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.subsystem.{HierarchicalElementCrossingParamsLike, CanAttachTile}
 import freechips.rocketchip.util._
-import freechips.rocketchip.prci.{ClockSinkParameters}
+import freechips.rocketchip.prci.{ClockSinkParameters, ClockCrossingType}
 
 // =======
 // Outline

diff --git a/src/main/scala/interrupts/CrossingHelper.scala b/src/main/scala/interrupts/CrossingHelper.scala
@@ -5,8 +5,7 @@ package freechips.rocketchip.interrupts
 import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{CrossingType, ClockCrossingType, NoCrossing, AsynchronousCrossing, RationalCrossing, SynchronousCrossing, CreditedCrossing}
-import freechips.rocketchip.prci.{ResetCrossingType, NoResetCrossing, StretchedResetCrossing}
+import freechips.rocketchip.prci.{ResetCrossingType, NoResetCrossing, StretchedResetCrossing, CrossingType, ClockCrossingType, NoCrossing, AsynchronousCrossing, RationalCrossing, SynchronousCrossing, CreditedCrossing}
 import freechips.rocketchip.util.CreditedDelay
 
 trait IntOutwardCrossingHelper {

diff --git a/src/main/scala/interrupts/package.scala b/src/main/scala/interrupts/package.scala
@@ -7,8 +7,7 @@ import chisel3._
 import org.chipsalliance.diplomacy._
 import org.chipsalliance.diplomacy.nodes._
 
-import freechips.rocketchip.diplomacy.HasClockDomainCrossing
-import freechips.rocketchip.prci.HasResetDomainCrossing
+import freechips.rocketchip.prci.{HasClockDomainCrossing, HasResetDomainCrossing}
 
 package object interrupts
 {

diff --git a/src/main/scala/diplomacy/ClockDomain.scala → src/main/scala/prci/ClockCrossingType.scala b/src/main/scala/diplomacy/ClockDomain.scala → src/main/scala/prci/ClockCrossingType.scala
@@ -1,10 +1,10 @@
 // See LICENSE.SiFive for license details.
 
-package freechips.rocketchip.diplomacy
+package freechips.rocketchip.prci
+import org.chipsalliance.diplomacy.lazymodule.{LazyScope, LazyModule}
+import freechips.rocketchip.diplomacy.{BufferParams}
 import freechips.rocketchip.util.{RationalDirection, FastToSlow, AsyncQueueParams, CreditedDelay}
 
-// TODO this should all be moved to package freechips.rocketchip.prci now that it exists
-
 trait CrossingType
 
 trait HasDomainCrossing extends LazyScope { this: LazyModule =>

diff --git a/src/main/scala/prci/ClockDomain.scala b/src/main/scala/prci/ClockDomain.scala
@@ -6,8 +6,6 @@ import org.chipsalliance.cde.config._
 
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{HasClockDomainCrossing, HasDomainCrossing}
-
 abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
 {
   def clockBundle: ClockBundle

diff --git a/src/main/scala/prci/IOHelper.scala b/src/main/scala/prci/IOHelper.scala
@@ -6,8 +6,6 @@ import chisel3._
 
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{ClockCrossingType, SynchronousCrossing}
-
 object IOHelper {
 
   def forNonSynchronous[T <: Data](gen: => T, xs: Seq[ClockCrossingType], prefix: String): Seq[Option[ModuleValue[T]]] = {

diff --git a/src/main/scala/prci/ResetCrossingType.scala b/src/main/scala/prci/ResetCrossingType.scala
@@ -4,8 +4,6 @@ package freechips.rocketchip.prci
 import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{CrossingType, HasDomainCrossing}
-
 trait HasResetDomainCrossing extends HasDomainCrossing { this: LazyModule =>
   type DomainCrossingType = ResetCrossingType
 }

diff --git a/src/main/scala/prci/package.scala b/src/main/scala/prci/package.scala
@@ -3,8 +3,7 @@
 package freechips.rocketchip
 
 import org.chipsalliance.diplomacy.nodes._
-
-import freechips.rocketchip.diplomacy.{ClockCrossingType, AsynchronousCrossing}
+import freechips.rocketchip.diplomacy.{BufferParams}
 
 package object prci
 {
@@ -18,4 +17,6 @@ package object prci
     case _: AsynchronousCrossing => async
     case _ => notasync
   }
+
+  implicit def noCrossing(value: NoCrossing.type): ClockCrossingType = SynchronousCrossing(BufferParams.none)
 }
diff --git a/src/main/scala/regmapper/RegisterRouter.scala b/src/main/scala/regmapper/RegisterRouter.scala
@@ -9,7 +9,9 @@ import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.bundlebridge._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{AddressSet, Description, Device, SimpleDevice, ResourceBindings, ResourceValue, HasClockDomainCrossing}
+import freechips.rocketchip.diplomacy.{AddressSet, Description, Device, SimpleDevice, ResourceBindings, ResourceValue}
+import freechips.rocketchip.prci.{HasClockDomainCrossing}
+
 
 /** Parameters which apply to any RegisterRouter. */
 case class RegisterRouterParams(

diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala
@@ -9,7 +9,8 @@ import chisel3.experimental.SourceInfo
 import org.chipsalliance.cde.config._
 
 import freechips.rocketchip.amba.AMBAProt
-import freechips.rocketchip.diplomacy.{ClockCrossingType, RationalCrossing, SynchronousCrossing, BufferParams, AsynchronousCrossing, CreditedCrossing}
+import freechips.rocketchip.diplomacy.{BufferParams}
+import freechips.rocketchip.prci.{ClockCrossingType, RationalCrossing, SynchronousCrossing, AsynchronousCrossing, CreditedCrossing}
 import freechips.rocketchip.tile.{CoreBundle, LookupByHartId}
 import freechips.rocketchip.tilelink.{TLFIFOFixer,ClientMetadata, TLBundleA, TLAtomics, TLBundleB, TLPermissions}
 import freechips.rocketchip.tilelink.TLMessages.{AccessAck, HintAck, AccessAckData, Grant, GrantData, ReleaseAck}

diff --git a/src/main/scala/subsystem/BusTopology.scala b/src/main/scala/subsystem/BusTopology.scala
@@ -5,7 +5,7 @@ package freechips.rocketchip.subsystem
 import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.nodes._
 
-import freechips.rocketchip.diplomacy.{ClockCrossingType, NoCrossing, SynchronousCrossing}
+import freechips.rocketchip.prci.{ClockCrossingType, NoCrossing, SynchronousCrossing}
 import freechips.rocketchip.tilelink.{TLBusWrapper, TLBusWrapperTopology, TLBusWrapperConnection}
 import freechips.rocketchip.util.Location
 

diff --git a/src/main/scala/subsystem/Cluster.scala b/src/main/scala/subsystem/Cluster.scala
@@ -8,9 +8,9 @@ import org.chipsalliance.diplomacy.bundlebridge._
 import org.chipsalliance.diplomacy.lazymodule._
 
 import freechips.rocketchip.devices.debug.{TLDebugModule}
-import freechips.rocketchip.diplomacy.{ClockCrossingType, NoCrossing, FlipRendering}
+import freechips.rocketchip.diplomacy.{FlipRendering}
 import freechips.rocketchip.interrupts.{IntIdentityNode, IntSyncIdentityNode, NullIntSource}
-import freechips.rocketchip.prci.{ClockSinkParameters, ClockGroupIdentityNode, BundleBridgeBlockDuringReset}
+import freechips.rocketchip.prci.{ClockCrossingType, NoCrossing, ClockSinkParameters, ClockGroupIdentityNode, BundleBridgeBlockDuringReset}
 import freechips.rocketchip.tile.{RocketTile, NMI, TraceBundle}
 import freechips.rocketchip.tilelink.TLWidthWidget
 import freechips.rocketchip.util.TraceCoreInterface

diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala
@@ -12,9 +12,10 @@ import freechips.rocketchip.devices.debug.{DebugModuleKey, DefaultDebugModulePar
 import freechips.rocketchip.devices.tilelink.{
   BuiltInErrorDeviceParams, BootROMLocated, BootROMParams, CLINTKey, DevNullDevice, CLINTParams, PLICKey, PLICParams, DevNullParams
 }
+import freechips.rocketchip.prci.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing, ClockCrossingType}
 import freechips.rocketchip.diplomacy.{
-  AddressSet, SynchronousCrossing, AsynchronousCrossing, RationalCrossing, MonitorsEnabled,
-  DTSModel, DTSCompat, DTSTimebase, ClockCrossingType, BigIntHexContext
+  AddressSet, MonitorsEnabled,
+  DTSModel, DTSCompat, DTSTimebase, BigIntHexContext
 }
 import freechips.rocketchip.rocket.{PgLevels, RocketCoreParams, MulDivParams, DCacheParams, ICacheParams, BTBParams, DebugROBParams}
 import freechips.rocketchip.tile.{

diff --git a/src/main/scala/subsystem/CrossingWrapper.scala b/src/main/scala/subsystem/CrossingWrapper.scala
@@ -6,7 +6,7 @@ import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
 import freechips.rocketchip.amba.axi4.{AXI4InwardNode, AXI4OutwardNode}
-import freechips.rocketchip.diplomacy.{ClockCrossingType, HasClockDomainCrossing}
+import freechips.rocketchip.prci.{ClockCrossingType, HasClockDomainCrossing}
 import freechips.rocketchip.tilelink.{TLInwardNode, TLOutwardNode}
 import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode}
 import freechips.rocketchip.prci.{HasResetDomainCrossing, ResetCrossingType}

diff --git a/src/main/scala/subsystem/HasHierarchicalElements.scala b/src/main/scala/subsystem/HasHierarchicalElements.scala
@@ -10,14 +10,13 @@ import org.chipsalliance.diplomacy.lazymodule._
 
 import freechips.rocketchip.devices.debug.{TLDebugModule, HasPeripheryDebug}
 import freechips.rocketchip.devices.tilelink.{BasicBusBlocker, BasicBusBlockerParams, CLINT, TLPLIC, CLINTConsts}
-import freechips.rocketchip.diplomacy.ClockCrossingType
 import freechips.rocketchip.interrupts.{
   IntNode, IntSyncNode, IntEphemeralNode, NullIntSource, IntNexusNode, IntSourcePortParameters,
   IntSourceParameters, IntSinkPortParameters, IntSinkParameters, IntSyncIdentityNode, NullIntSyncSource
 }
 import freechips.rocketchip.tile.{TileParams, TilePRCIDomain, BaseTile, NMI, TraceBundle}
 import freechips.rocketchip.tilelink.{TLNode, TLBuffer, TLCacheCork, TLTempNode, TLFragmenter}
-import freechips.rocketchip.prci.{ClockGroup, ResetCrossingType, ClockGroupNode, ClockDomain}
+import freechips.rocketchip.prci.{ClockCrossingType, ClockGroup, ResetCrossingType, ClockGroupNode, ClockDomain}
 import freechips.rocketchip.rocket.TracedInstruction
 import freechips.rocketchip.util.TraceCoreInterface
 

diff --git a/src/main/scala/subsystem/HasTiles.scala b/src/main/scala/subsystem/HasTiles.scala
@@ -9,11 +9,11 @@ import org.chipsalliance.diplomacy.bundlebridge._
 import org.chipsalliance.diplomacy.lazymodule._
 
 import freechips.rocketchip.devices.debug.TLDebugModule
-import freechips.rocketchip.diplomacy.{DisableMonitors, NoCrossing, SynchronousCrossing, CreditedCrossing, RationalCrossing, AsynchronousCrossing, FlipRendering}
+import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering}
 import freechips.rocketchip.interrupts.{IntXbar, IntSinkNode, IntSinkPortSimple, IntSyncAsyncCrossingSink}
 import freechips.rocketchip.tile.{MaxHartIdBits, BaseTile, InstantiableTileParams, TileParams, TilePRCIDomain, TraceBundle, PriorityMuxHartIdFromSeq}
 import freechips.rocketchip.tilelink.TLWidthWidget
-import freechips.rocketchip.prci.{ClockGroup, BundleBridgeBlockDuringReset}
+import freechips.rocketchip.prci.{ClockGroup, BundleBridgeBlockDuringReset, NoCrossing, SynchronousCrossing, CreditedCrossing, RationalCrossing, AsynchronousCrossing}
 import freechips.rocketchip.rocket.TracedInstruction
 import freechips.rocketchip.util.TraceCoreInterface
 

diff --git a/src/main/scala/subsystem/HierarchicalElement.scala b/src/main/scala/subsystem/HierarchicalElement.scala
@@ -7,9 +7,9 @@ import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
 import freechips.rocketchip.devices.debug.TLDebugModule
-import freechips.rocketchip.diplomacy.{BufferParams, ClockCrossingType}
+import freechips.rocketchip.diplomacy.{BufferParams}
 import freechips.rocketchip.interrupts.IntXbar
-import freechips.rocketchip.prci.{ClockSinkParameters, ResetCrossingType}
+import freechips.rocketchip.prci.{ClockSinkParameters, ResetCrossingType, ClockCrossingType}
 import freechips.rocketchip.tile.{LookupByHartIdImpl, TraceBundle}
 import freechips.rocketchip.tilelink.{TLNode, TLIdentityNode, TLXbar, TLBuffer, TLInwardNode, TLOutwardNode}
 

diff --git a/src/main/scala/subsystem/HierarchicalElementPRCIDomain.scala b/src/main/scala/subsystem/HierarchicalElementPRCIDomain.scala
@@ -7,9 +7,9 @@ import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
 import freechips.rocketchip.devices.debug.TLDebugModule
-import freechips.rocketchip.diplomacy.{ClockCrossingType, DisableMonitors, FlipRendering}
+import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering}
 import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode}
-import freechips.rocketchip.prci.{ResetCrossingType, ResetDomain, ClockSinkNode, ClockSinkParameters, ClockIdentityNode, FixedClockBroadcast, ClockDomain}
+import freechips.rocketchip.prci.{ClockCrossingType, ResetCrossingType, ResetDomain, ClockSinkNode, ClockSinkParameters, ClockIdentityNode, FixedClockBroadcast, ClockDomain}
 import freechips.rocketchip.tile.{RocketTile, TraceBundle}
 import freechips.rocketchip.tilelink.{TLInwardNode, TLOutwardNode}
 import freechips.rocketchip.util.TraceCoreInterface

diff --git a/src/main/scala/subsystem/InterruptBus.scala b/src/main/scala/subsystem/InterruptBus.scala
@@ -7,9 +7,9 @@ import chisel3._
 import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{ClockCrossingType, AsynchronousCrossing, RationalCrossing, Device, DeviceInterrupts, Description, ResourceBindings}
+import freechips.rocketchip.diplomacy.{Device, DeviceInterrupts, Description, ResourceBindings}
 import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode, IntXbar, IntNameNode, IntSourceNode, IntSourcePortSimple}
-import freechips.rocketchip.prci.ClockSinkDomain
+import freechips.rocketchip.prci.{ClockCrossingType, AsynchronousCrossing, RationalCrossing, ClockSinkDomain}
 
 import freechips.rocketchip.interrupts.IntClockDomainCrossing
 

diff --git a/src/main/scala/subsystem/RocketSubsystem.scala b/src/main/scala/subsystem/RocketSubsystem.scala
@@ -6,8 +6,7 @@ import org.chipsalliance.cde.config._
 
 import freechips.rocketchip.devices.debug.HasPeripheryDebug
 import freechips.rocketchip.devices.tilelink.{CanHavePeripheryCLINT, CanHavePeripheryPLIC}
-import freechips.rocketchip.diplomacy.{SynchronousCrossing, ClockCrossingType}
-import freechips.rocketchip.prci.{ResetCrossingType, NoResetCrossing}
+import freechips.rocketchip.prci.{ResetCrossingType, NoResetCrossing, SynchronousCrossing, ClockCrossingType}
 import freechips.rocketchip.tile.{RocketTile, RocketTileParams}
 import freechips.rocketchip.util.HasCoreMonitorBundles
 

diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala
@@ -10,15 +10,15 @@ import org.chipsalliance.diplomacy._
 import org.chipsalliance.diplomacy.bundlebridge._
 
 
-import freechips.rocketchip.diplomacy.{ClockCrossingType, PropertyMap, PropertyOption, ResourceReference, DTSTimebase}
+import freechips.rocketchip.diplomacy.{PropertyMap, PropertyOption, ResourceReference, DTSTimebase}
 import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode}
 import freechips.rocketchip.rocket.{ICacheParams, DCacheParams, BTBParams, PgLevels, ASIdBits, VMIdBits, TraceAux, BPWatch}
 import freechips.rocketchip.subsystem.{
   HierarchicalElementParams, InstantiableHierarchicalElementParams, HierarchicalElementCrossingParamsLike,
   CacheBlockBytes, SystemBusKey, BaseHierarchicalElement, InsertTimingClosureRegistersOnHartIds, BaseHierarchicalElementModuleImp
 }
 import freechips.rocketchip.tilelink.{TLEphemeralNode, TLOutwardNode, TLNode, TLFragmenter, EarlyAck, TLWidthWidget, TLManagerParameters, ManagerUnification}
-import freechips.rocketchip.prci.ClockSinkParameters
+import freechips.rocketchip.prci.{ClockCrossingType, ClockSinkParameters}
 import freechips.rocketchip.util.{TraceCoreParams, TraceCoreInterface}
 
 import freechips.rocketchip.diplomacy.BigIntToProperty

diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
@@ -10,9 +10,9 @@ import org.chipsalliance.diplomacy.lazymodule._
 
 import freechips.rocketchip.devices.tilelink.{BasicBusBlockerParams, BasicBusBlocker}
 import freechips.rocketchip.diplomacy.{
-  AddressSet, ClockCrossingType, DisableMonitors, SimpleDevice, Description,
+  AddressSet, DisableMonitors, SimpleDevice, Description,
   ResourceAnchors, ResourceBindings, ResourceBinding, Resource, ResourceAddress,
-  RationalCrossing, BufferParams
+  BufferParams
 }
 import freechips.rocketchip.interrupts.IntIdentityNode
 import freechips.rocketchip.tilelink.{TLIdentityNode, TLBuffer}
@@ -21,7 +21,7 @@ import freechips.rocketchip.rocket.{
   HasICacheFrontend, ScratchpadSlavePort, HasICacheFrontendModule, Rocket
 }
 import freechips.rocketchip.subsystem.HierarchicalElementCrossingParamsLike
-import freechips.rocketchip.prci.ClockSinkParameters
+import freechips.rocketchip.prci.{ClockSinkParameters, RationalCrossing, ClockCrossingType}
 import freechips.rocketchip.util.{Annotated, InOrderArbiter}
 
 import freechips.rocketchip.util.BooleanToAugmentedBoolean

diff --git a/src/main/scala/tilelink/AsyncCrossing.scala b/src/main/scala/tilelink/AsyncCrossing.scala
@@ -7,7 +7,8 @@ import chisel3._
 import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{AddressSet, AsynchronousCrossing, NodeHandle}
+import freechips.rocketchip.diplomacy.{AddressSet, NodeHandle}
+import freechips.rocketchip.prci.{AsynchronousCrossing}
 import freechips.rocketchip.subsystem.CrossingWrapper
 import freechips.rocketchip.util.{AsyncQueueParams, ToAsyncBundle, FromAsyncBundle, Pow2ClockDivider, property}