maintain same width of MIP CSR bit positions 'lip'

chipsalliance · Jun 9, 2021 · 80d3fec · 80d3fec
1 parent ae0b318
commit 80d3fec
Showing 1 changed file with 1 addition and 2 deletions.
diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala
@@ -96,9 +96,8 @@ class DCSR extends Bundle {
 class MIP(implicit p: Parameters) extends CoreBundle()(p)
     with HasCoreParameters {
   val lip = Vec(coreParams.nLocalInterrupts, Bool())
-  val zero2 = Bool()
-  val debug = Bool() // keep in sync with CSR.debugIntCause
   val zero1 = Bool()
+  val debug = Bool() // keep in sync with CSR.debugIntCause
   val rocc = Bool()
   val sgeip = Bool()
   val meip = Bool()