Rename L2 to LLC

chipsalliance · Sep 26, 2023 · 5b29fe9 · 5b29fe9
1 parent f478b45
commit 5b29fe9
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Showing 3 changed files with 9 additions and 9 deletions.
diff --git a/src/main/scala/subsystem/BankedCoherenceParams.scala b/src/main/scala/subsystem/BankedCoherenceParams.scala
@@ -14,7 +14,7 @@ import CoherenceManagerWrapper._
 /** Global cache coherence granularity, which applies to all caches, for now. */
 case object CacheBlockBytes extends Field[Int](64)
 
-/** L2 Broadcast Hub configuration */
+/** LLC Broadcast Hub configuration */
 case object BroadcastKey extends Field(BroadcastParams())
 
 case class BroadcastParams(

diff --git a/src/main/scala/subsystem/BusTopology.scala b/src/main/scala/subsystem/BusTopology.scala
@@ -28,7 +28,7 @@ case object PBUS extends TLBusWrapperLocation("subsystem_pbus")
 case object FBUS extends TLBusWrapperLocation("subsystem_fbus")
 case object MBUS extends TLBusWrapperLocation("subsystem_mbus")
 case object CBUS extends TLBusWrapperLocation("subsystem_cbus")
-case object L2   extends TLBusWrapperLocation("subsystem_l2")
+case object LLC  extends TLBusWrapperLocation("subsystem_llc")
 
 /** Parameterizes the subsystem in terms of optional clock-crossings
   *   that are insertable between some of the five traditional tilelink bus wrappers.
@@ -91,16 +91,16 @@ case class HierarchicalBusTopologyParams(
 case class CoherentBusTopologyParams(
   sbus: SystemBusParams, // TODO remove this after better width propagation
   mbus: MemoryBusParams,
-  l2: BankedCoherenceParams,
+  coherence: BankedCoherenceParams,
   sbusToMbusXType: ClockCrossingType = NoCrossing,
   driveMBusClockFromSBus: Boolean = true
 ) extends TLBusWrapperTopology(
-  instantiations = (if (l2.nBanks == 0) Nil else List(
+  instantiations = (if (coherence.nBanks == 0) Nil else List(
     (MBUS, mbus),
-    (L2, CoherenceManagerWrapperParams(mbus.blockBytes, mbus.beatBytes, l2.nBanks, L2.name, sbus.dtsFrequency)(l2.coherenceManager)))),
-  connections = if (l2.nBanks == 0) Nil else List(
-    (SBUS, L2,   TLBusWrapperConnection(driveClockFromMaster = Some(true), nodeBinding = BIND_STAR)()),
-    (L2,  MBUS,  TLBusWrapperConnection.crossTo(
+    (LLC, CoherenceManagerWrapperParams(mbus.blockBytes, mbus.beatBytes, coherence.nBanks, LLC.name, sbus.dtsFrequency)(coherence.coherenceManager)))),
+  connections = if (coherence.nBanks == 0) Nil else List(
+    (SBUS, LLC,   TLBusWrapperConnection(driveClockFromMaster = Some(true), nodeBinding = BIND_STAR)()),
+    (LLC,  MBUS,  TLBusWrapperConnection.crossTo(
       xType = sbusToMbusXType,
       driveClockFromMaster = if (driveMBusClockFromSBus) Some(true) else None,
       nodeBinding = BIND_QUERY))

diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala
@@ -84,7 +84,7 @@ class WithCoherentBusTopology extends Config((site, here, up) => {
     CoherentBusTopologyParams(
       sbus = site(SystemBusKey),
       mbus = site(MemoryBusKey),
-      l2 = site(BankedCoherenceKey),
+      coherence = site(BankedCoherenceKey),
       sbusToMbusXType = site(SbusToMbusXTypeKey),
       driveMBusClockFromSBus = site(DriveClocksFromSBus)))
 })