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Switch to SortedMap for tile node maps
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@jerryz123
jerryz123 committed Oct 16, 2023
1 parent 8f220f1 commit 516288f
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Showing 3 changed files with 51 additions and 51 deletions.
26 changes: 13 additions & 13 deletions src/main/scala/subsystem/Cluster.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.debug.{TLDebugModule}
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import scala.collection.immutable.SortedMap

case class ClustersLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachCluster]](Nil)

Expand Down Expand Up @@ -58,17 +58,17 @@ class Cluster(
lazy val ibus = LazyModule(new InterruptBusWrapper)
ibus.clockNode := csbus.fixedClockNode

lazy val msipNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.to(ListMap)
lazy val meipNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.to(ListMap)
lazy val seipNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.to(ListMap)
lazy val tileToPlicNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.to(ListMap)
lazy val debugNodes = totalTileIdList.map { i => (i, IntSyncIdentityNode()) }.to(ListMap)
lazy val msipNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.to(SortedMap)
lazy val meipNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.to(SortedMap)
lazy val seipNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.to(SortedMap)
lazy val tileToPlicNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.to(SortedMap)
lazy val debugNodes = totalTileIdList.map { i => (i, IntSyncIdentityNode()) }.to(SortedMap)
lazy val nmiNodes = totalTiles.filter { case (i,t) => t.tileParams.core.useNMI }
.mapValues(_ => BundleBridgeIdentityNode[NMI]()).to(ListMap)
lazy val tileHartIdNodes = totalTileIdList.map { i => (i, BundleBridgeIdentityNode[UInt]()) }.to(ListMap)
lazy val tileResetVectorNodes = totalTileIdList.map { i => (i, BundleBridgeIdentityNode[UInt]()) }.to(ListMap)
lazy val traceCoreNodes = totalTileIdList.map { i => (i, BundleBridgeIdentityNode[TraceCoreInterface]()) }.to(ListMap)
lazy val traceNodes = totalTileIdList.map { i => (i, BundleBridgeIdentityNode[TraceBundle]()) }.to(ListMap)
.mapValues(_ => BundleBridgeIdentityNode[NMI]()).to(SortedMap)
lazy val tileHartIdNodes = totalTileIdList.map { i => (i, BundleBridgeIdentityNode[UInt]()) }.to(SortedMap)
lazy val tileResetVectorNodes = totalTileIdList.map { i => (i, BundleBridgeIdentityNode[UInt]()) }.to(SortedMap)
lazy val traceCoreNodes = totalTileIdList.map { i => (i, BundleBridgeIdentityNode[TraceCoreInterface]()) }.to(SortedMap)
lazy val traceNodes = totalTileIdList.map { i => (i, BundleBridgeIdentityNode[TraceBundle]()) }.to(SortedMap)

// TODO fix: shouldn't need to connect dummy notifications
tileHaltXbarNode := NullIntSource()
Expand Down Expand Up @@ -103,7 +103,7 @@ trait CanAttachCluster {
def clusterParams: ClusterParams
def crossingParams: HierarchicalElementCrossingParamsLike

def instantiate(allClusterParams: Seq[ClusterParams], instantiatedClusters: ListMap[Int, ClusterPRCIDomain])(implicit p: Parameters): ClusterPRCIDomain = {
def instantiate(allClusterParams: Seq[ClusterParams], instantiatedClusters: SortedMap[Int, ClusterPRCIDomain])(implicit p: Parameters): ClusterPRCIDomain = {
val clockSinkParams = clusterParams.clockSinkParams.copy(name = Some(clusterParams.uniqueName))
val cluster_prci_domain = LazyModule(new ClusterPRCIDomain(
clockSinkParams, crossingParams, clusterParams, PriorityMuxClusterIdFromSeq(allClusterParams)))
Expand Down Expand Up @@ -218,7 +218,7 @@ case class CloneClusterAttachParams(
def clusterParams = cloneParams.clusterParams
def crossingParams = cloneParams.crossingParams

override def instantiate(allClusterParams: Seq[ClusterParams], instantiatedClusters: ListMap[Int, ClusterPRCIDomain])(implicit p: Parameters): ClusterPRCIDomain = {
override def instantiate(allClusterParams: Seq[ClusterParams], instantiatedClusters: SortedMap[Int, ClusterPRCIDomain])(implicit p: Parameters): ClusterPRCIDomain = {
require(instantiatedClusters.contains(sourceClusterId))
val clockSinkParams = clusterParams.clockSinkParams.copy(name = Some(clusterParams.uniqueName))
val cluster_prci_domain = CloneLazyModule(
Expand Down
62 changes: 31 additions & 31 deletions src/main/scala/subsystem/HasHierarchicalElements.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.prci.{ClockGroup, ResetCrossingType, ClockGroupNode}
import freechips.rocketchip.util._
import freechips.rocketchip.rocket.{TracedInstruction}
import scala.collection.immutable.ListMap
import scala.collection.immutable.SortedMap

/** A default implementation of parameterizing the connectivity of the port where the tile is the master.
* Optional timing buffers and/or an optional CacheCork can be inserted in the interconnect's clock domain.
Expand Down Expand Up @@ -67,28 +67,28 @@ trait InstantiatesHierarchicalElements { this: LazyModule with Attachable =>
val tileCrossingTypes: Seq[ClockCrossingType] = tileAttachParams.map(_.crossingParams.crossingType)

/** The actual list of instantiated tiles in this block. */
val tile_prci_domains: ListMap[Int, TilePRCIDomain[_]] = tileAttachParams.foldLeft(ListMap[Int, TilePRCIDomain[_]]()) {
val tile_prci_domains: SortedMap[Int, TilePRCIDomain[_]] = tileAttachParams.foldLeft(SortedMap[Int, TilePRCIDomain[_]]()) {
case (instantiated, params) => instantiated + (params.tileParams.tileId -> params.instantiate(tileParams, instantiated)(p))
}

val clusterAttachParams: Seq[CanAttachCluster] = p(ClustersLocated(location)).sortBy(_.clusterParams.clusterId)
val clusterParams: Seq[ClusterParams] = clusterAttachParams.map(_.clusterParams)
val clusterCrossingTypes: Seq[ClockCrossingType] = clusterAttachParams.map(_.crossingParams.crossingType)
val cluster_prci_domains: ListMap[Int, ClusterPRCIDomain] = clusterAttachParams.foldLeft(ListMap[Int, ClusterPRCIDomain]()) {
val cluster_prci_domains: SortedMap[Int, ClusterPRCIDomain] = clusterAttachParams.foldLeft(SortedMap[Int, ClusterPRCIDomain]()) {
case (instantiated, params) => instantiated + (params.clusterParams.clusterId -> params.instantiate(clusterParams, instantiated)(p))
}

val element_prci_domains: Seq[HierarchicalElementPRCIDomain[_]] = tile_prci_domains.values.toSeq ++ cluster_prci_domains.values.toSeq

val leafTiles: ListMap[Int, BaseTile] = tile_prci_domains.mapValues(_.element.asInstanceOf[BaseTile]).to(ListMap)
val totalTiles: ListMap[Int, BaseTile] = (leafTiles ++ cluster_prci_domains.values.map(_.element.totalTiles).flatten)
val leafTiles: SortedMap[Int, BaseTile] = SortedMap(tile_prci_domains.mapValues(_.element.asInstanceOf[BaseTile]).toSeq.sortBy(_._1):_*)
val totalTiles: SortedMap[Int, BaseTile] = (leafTiles ++ cluster_prci_domains.values.map(_.element.totalTiles).flatten)

// Helper functions for accessing certain parameters that are popular to refer to in subsystem code
def nLeafTiles: Int = leafTiles.size
def nTotalTiles: Int = totalTiles.size
def leafTileIdList: Seq[Int] = leafTiles.keys.toSeq.sorted
def totalTileIdList: Seq[Int] = totalTiles.keys.toSeq.sorted
def localIntCounts: ListMap[Int, Int] = totalTiles.mapValues(_.tileParams.core.nLocalInterrupts).to(ListMap)
def localIntCounts: SortedMap[Int, Int] = totalTiles.mapValues(_.tileParams.core.nLocalInterrupts).to(SortedMap)

require(totalTileIdList.distinct.size == totalTiles.size, s"Every tile must be statically assigned a unique id, but got:\n${totalTileIdList}")
}
Expand Down Expand Up @@ -142,16 +142,16 @@ trait DefaultHierarchicalElementContextType
extends Attachable
with HasTileNotificationSinks
{ this: LazyModule with Attachable =>
val msipNodes: ListMap[Int, IntNode]
val meipNodes: ListMap[Int, IntNode]
val seipNodes: ListMap[Int, IntNode]
val tileToPlicNodes: ListMap[Int, IntNode]
val debugNodes: ListMap[Int, IntSyncNode]
val nmiNodes: ListMap[Int, BundleBridgeNode[NMI]]
val tileHartIdNodes: ListMap[Int, BundleBridgeNode[UInt]]
val tileResetVectorNodes: ListMap[Int, BundleBridgeNode[UInt]]
val traceCoreNodes: ListMap[Int, BundleBridgeNode[TraceCoreInterface]]
val traceNodes: ListMap[Int, BundleBridgeNode[TraceBundle]]
val msipNodes: SortedMap[Int, IntNode]
val meipNodes: SortedMap[Int, IntNode]
val seipNodes: SortedMap[Int, IntNode]
val tileToPlicNodes: SortedMap[Int, IntNode]
val debugNodes: SortedMap[Int, IntSyncNode]
val nmiNodes: SortedMap[Int, BundleBridgeNode[NMI]]
val tileHartIdNodes: SortedMap[Int, BundleBridgeNode[UInt]]
val tileResetVectorNodes: SortedMap[Int, BundleBridgeNode[UInt]]
val traceCoreNodes: SortedMap[Int, BundleBridgeNode[TraceCoreInterface]]
val traceNodes: SortedMap[Int, BundleBridgeNode[TraceBundle]]
}

/** This trait provides the tile attachment context for the root (outermost) subsystem */
Expand All @@ -164,9 +164,9 @@ trait HasHierarchicalElementsRootContext
val plicOpt: Option[TLPLIC]
val debugOpt: Option[TLDebugModule]

val msipNodes: ListMap[Int, IntNode] = (0 until nTotalTiles).map { i =>
val msipNodes: SortedMap[Int, IntNode] = (0 until nTotalTiles).map { i =>
(i, IntEphemeralNode())
}.to(ListMap)
}.to(SortedMap)
msipNodes.foreach {
_._2 := clintOpt.map(_.intnode).getOrElse(NullIntSource(sources = CLINTConsts.ints))
}
Expand All @@ -176,36 +176,36 @@ trait HasHierarchicalElementsRootContext
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
outputRequiresInput = false,
inputRequiresOutput = false))
val meipNodes: ListMap[Int, IntNode] = (0 until nTotalTiles).map { i =>
val meipNodes: SortedMap[Int, IntNode] = (0 until nTotalTiles).map { i =>
(i, IntEphemeralNode() := plicOpt.map(_.intnode).getOrElse(meipIONode.get))
}.to(ListMap)
}.to(SortedMap)

val seipIONode = Option.when(plicOpt.isEmpty)(IntNexusNode(
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
outputRequiresInput = false,
inputRequiresOutput = false))
val seipNodes: ListMap[Int, IntNode] = totalTiles.filter { case (_, t) => t.tileParams.core.hasSupervisorMode }
.mapValues( _ => IntEphemeralNode() := plicOpt.map(_.intnode).getOrElse(seipIONode.get)).to(ListMap)
val seipNodes: SortedMap[Int, IntNode] = totalTiles.filter { case (_, t) => t.tileParams.core.hasSupervisorMode }
.mapValues( _ => IntEphemeralNode() := plicOpt.map(_.intnode).getOrElse(seipIONode.get)).to(SortedMap)

val tileToPlicNodes: ListMap[Int, IntNode] = (0 until nTotalTiles).map { i =>
val tileToPlicNodes: SortedMap[Int, IntNode] = (0 until nTotalTiles).map { i =>
plicOpt.map(o => (i, o.intnode :=* IntEphemeralNode()))
}.flatten.to(ListMap)
}.flatten.to(SortedMap)

val debugNodes: ListMap[Int, IntSyncNode] = (0 until nTotalTiles).map { i =>
val debugNodes: SortedMap[Int, IntSyncNode] = (0 until nTotalTiles).map { i =>
(i, IntSyncIdentityNode())
}.to(ListMap)
}.to(SortedMap)

debugNodes.foreach { case (hartid, node) =>
node := debugOpt.map(_.intnode).getOrElse(IntSyncCrossingSource() := NullIntSource())
}

val nmiHarts = totalTiles.filter { case (_, t) => t.tileParams.core.useNMI }.keys
val nmiIONodes = nmiHarts.map { i => (i, BundleBridgeSource[NMI]()) }.to(ListMap)
val nmiNodes: ListMap[Int, BundleBridgeNode[NMI]] = nmiIONodes.map { case (i, n) =>
val nmiIONodes = nmiHarts.map { i => (i, BundleBridgeSource[NMI]()) }.to(SortedMap)
val nmiNodes: SortedMap[Int, BundleBridgeNode[NMI]] = nmiIONodes.map { case (i, n) =>
(i, BundleBridgeEphemeralNode[NMI]() := n)
}.to(ListMap)
}.to(SortedMap)

val traceCoreNodes: ListMap[Int, BundleBridgeSink[TraceCoreInterface]] = (0 until nTotalTiles).map { i => (i, BundleBridgeSink[TraceCoreInterface]()) }.to(ListMap)
val traceNodes: ListMap[Int, BundleBridgeSink[TraceBundle]] = (0 until nTotalTiles).map { i => (i, BundleBridgeSink[TraceBundle]()) }.to(ListMap)
val traceCoreNodes: SortedMap[Int, BundleBridgeSink[TraceCoreInterface]] = (0 until nTotalTiles).map { i => (i, BundleBridgeSink[TraceCoreInterface]()) }.to(SortedMap)
val traceNodes: SortedMap[Int, BundleBridgeSink[TraceBundle]] = (0 until nTotalTiles).map { i => (i, BundleBridgeSink[TraceBundle]()) }.to(SortedMap)
}
14 changes: 7 additions & 7 deletions src/main/scala/subsystem/HasTiles.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.prci._
import freechips.rocketchip.util._
import freechips.rocketchip.rocket.{TracedInstruction}
import scala.collection.immutable.ListMap
import scala.collection.immutable.SortedMap

/** Entry point for Config-uring the presence of Tiles */
case class TilesLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachTile]](Nil)
Expand Down Expand Up @@ -53,9 +53,9 @@ case object HasTilesExternalResetVectorKey extends Field[Boolean](true)
*/
trait HasTileInputConstants { this: LazyModule with Attachable with InstantiatesHierarchicalElements =>
/** tileHartIdNode is used to collect publishers and subscribers of hartids. */
val tileHartIdNodes: ListMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i =>
val tileHartIdNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i =>
(i, BundleBridgeEphemeralNode[UInt]())
}.to(ListMap)
}.to(SortedMap)

/** tileHartIdNexusNode is a BundleBridgeNexus that collects dynamic hart prefixes.
*
Expand All @@ -82,9 +82,9 @@ trait HasTileInputConstants { this: LazyModule with Attachable with Instantiates
// TODO: Replace the DebugModuleHartSelFuncs config key with logic to consume the dynamic hart IDs

/** tileResetVectorNode is used to collect publishers and subscribers of tile reset vector addresses. */
val tileResetVectorNodes: ListMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i =>
val tileResetVectorNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i =>
(i, BundleBridgeEphemeralNode[UInt]())
}.to(ListMap)
}.to(SortedMap)

/** tileResetVectorNexusNode is a BundleBridgeNexus that accepts a single reset vector source, and broadcasts it to all tiles. */
val tileResetVectorNexusNode = BundleBroadcast[UInt](
Expand Down Expand Up @@ -155,7 +155,7 @@ trait CanAttachTile {
def crossingParams: HierarchicalElementCrossingParamsLike

/** Narrow waist through which all tiles are intended to pass while being instantiated. */
def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: ListMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = {
def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = {
val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName))
val tile_prci_domain = LazyModule(new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self =>
val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) }
Expand Down Expand Up @@ -302,7 +302,7 @@ case class CloneTileAttachParams(
def tileParams = cloneParams.tileParams
def crossingParams = cloneParams.crossingParams

override def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: ListMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = {
override def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = {
require(instantiatedTiles.contains(sourceTileId))
val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName))
val tile_prci_domain = CloneLazyModule(
Expand Down

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