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chipsalliance · Sep 30, 2023 · 35bfcb1 · 35bfcb1
1 parent d016127
commit 35bfcb1
Showing 1 changed file with 4 additions and 5 deletions.
diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
@@ -213,12 +213,9 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
           case s if s.contains("rv_zfh") => minFLen == 16
           case s if s.contains("rv64_zfh") => (xLen == 64) && (minFLen == 16)
           case s if s.contains("rv_d_zfh") => (fLen == 64) && (minFLen == 16)
+
           // Priv
-          case s if s.contains("rv_system") => i.name match {
-            case "wfi" => true
-            case "mret" => true
-            case "dret" => usingDebug
-          }
+          case s if s.contains("rv_system") => true
           // Supervisor
           case s if s.contains("rv_s") => i.name match {
             // if support superviosr but don't support virtual memory, raise illinstr.
@@ -229,6 +226,8 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
           // Hypervisor
           case s if s.contains("rv_h") => usingHypervisor
           case s if s.contains("rv64_h") => (xLen == 64) && usingHypervisor
+          // Debug
+          case s if s.contains("rv_sdext") => usingDebug
 
           // TODO:
           //   Bit Manipulation, RocketChip doesn't provide a fine-grand Bit-Manipulation and Crypto support for now.