DebugROB params

chipsalliance · Jan 20, 2024 · 2974eca · 2974eca
1 parent 3588938
commit 2974eca
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Showing 4 changed files with 43 additions and 38 deletions.
diff --git a/src/main/scala/rocket/DebugROB.scala b/src/main/scala/rocket/DebugROB.scala
@@ -9,8 +9,8 @@ import chisel3.experimental.{IntParam}
 import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tile.{HasCoreParameters}
 import freechips.rocketchip.util.DecoupledHelper
-import midas.targetutils.SynthesizePrintf
 
+case class DebugROBParams(size: Int)
 
 class WidenedTracedInstruction extends Bundle {
   val valid = Bool()
@@ -116,7 +116,9 @@ class TaggedWbData(implicit val p: Parameters) extends Bundle with HasCoreParame
   val data  = UInt(xLen.W)
 }
 
-class HardDebugROB(val nXPR: Int)(implicit val p: Parameters) extends Module with HasCoreParameters {
+class HardDebugROB(val traceRatio: Int, val nXPR: Int)(implicit val p: Parameters)
+  extends Module with HasCoreParameters
+{
   val io = IO(new Bundle {
     val i_insn    = Input(new TracedInstruction)
     val should_wb = Input(Bool())
@@ -130,7 +132,7 @@ class HardDebugROB(val nXPR: Int)(implicit val p: Parameters) extends Module wit
     val o_insn   = Output(new TracedInstruction)
   })
 
-  val iq = Module(new Queue(new TaggedInstruction(nXPR), 32*nXPR, flow = true))
+  val iq = Module(new Queue(new TaggedInstruction(nXPR), traceRatio * nXPR, flow = true))
 
   // No backpressure
   assert(iq.io.enq.ready)
@@ -190,5 +192,4 @@ class HardDebugROB(val nXPR: Int)(implicit val p: Parameters) extends Module wit
   } .otherwise {
     qcnt := qcnt
   }
-  printf(SynthesizePrintf("qcnt: %d\n", qcnt))
 }
diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
@@ -48,10 +48,9 @@ case class RocketCoreParams(
   mimpid: Int = 0x20181004, // release date in BCD
   mulDiv: Option[MulDivParams] = Some(MulDivParams()),
   fpu: Option[FPUParams] = Some(FPUParams()),
-  debugROB: Boolean = false, // if enabled, uses a C++ debug ROB to generate trace-with-wdata
+  debugROB: Option[DebugROBParams] = None, // if size < 1, SW ROB, else HW ROB
   haveCease: Boolean = true, // non-standard CEASE instruction
   haveSimTimeout: Boolean = true, // add plusarg for simulation timeout
-  traceWdata: Boolean = false
 ) extends CoreParams {
   val lgPauseCycles = 5
   val haveFSDirty = false
@@ -62,7 +61,7 @@ case class RocketCoreParams(
   val retireWidth: Int = 1
   val instBits: Int = if (useCompressed) 16 else 32
   val lrscCycles: Int = 80 // worst case is 14 mispredicted branches + slop
-  val traceHasWdata: Boolean = traceWdata // ooo wb, so no wdata in trace
+  val traceHasWdata: Boolean = debugROB.isDefined // ooo wb, so no wdata in trace
   override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction
   override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32)
   override def customCSRs(implicit p: Parameters) = new RocketCustomCSRs
@@ -762,34 +761,37 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
   io.rocc.csrs <> csr.io.roccCSRs
   io.trace.time := csr.io.time
   io.trace.insns := csr.io.trace
-  if (rocketParams.debugROB) {
-    val csr_trace_with_wdata = WireInit(csr.io.trace(0))
-    csr_trace_with_wdata.wdata.get := rf_wdata
-    DebugROB.pushTrace(clock, reset,
-      io.hartid, csr_trace_with_wdata,
-      (wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception,
-      wb_ctrl.wxd && wb_wen && !wb_set_sboard,
-      wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U))
-
-    io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid)
-
-    DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata)
-  } else if (traceHasWdata) {
-    val csr_trace_with_wdata = WireInit(csr.io.trace(0))
-    csr_trace_with_wdata.wdata.get := rf_wdata
-
-    val debug_rob = Module(new HardDebugROB(32))
-    debug_rob.io.i_insn := csr_trace_with_wdata
-    debug_rob.io.should_wb := (wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) &&
-                              !csr.io.trace(0).exception
-    debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard
-    debug_rob.io.tag    := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)
-
-    debug_rob.io.wb_val  := ll_wen
-    debug_rob.io.wb_tag  := rf_waddr
-    debug_rob.io.wb_data := rf_wdata
-
-    io.trace.insns(0) := debug_rob.io.o_insn
+  if (rocketParams.debugROB.isDefined) {
+    val sz = rocketParams.debugROB.get.size
+    if (sz < 1) {
+      val csr_trace_with_wdata = WireInit(csr.io.trace(0))
+      csr_trace_with_wdata.wdata.get := rf_wdata
+      DebugROB.pushTrace(clock, reset,
+        io.hartid, csr_trace_with_wdata,
+        (wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception,
+        wb_ctrl.wxd && wb_wen && !wb_set_sboard,
+        wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U))
+
+      io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid)
+
+      DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata)
+    } else {
+      val csr_trace_with_wdata = WireInit(csr.io.trace(0))
+      csr_trace_with_wdata.wdata.get := rf_wdata
+
+      val debug_rob = Module(new HardDebugROB(sz, 32))
+      debug_rob.io.i_insn := csr_trace_with_wdata
+      debug_rob.io.should_wb := (wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) &&
+                                !csr.io.trace(0).exception
+      debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard
+      debug_rob.io.tag    := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)
+
+      debug_rob.io.wb_val  := ll_wen
+      debug_rob.io.wb_tag  := rf_waddr
+      debug_rob.io.wb_data := rf_wdata
+
+      io.trace.insns(0) := debug_rob.io.o_insn
+    }
   } else {
     io.trace.insns := csr.io.trace
   }

diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala
@@ -447,10 +447,10 @@ class WithFPUWithoutDivSqrt extends Config((site, here, up) => {
   }
 })
 
-class WithRocketDebugROB(enable: Boolean = true) extends Config((site, here, up) => {
+class WithRocketDebugROB(size: Int = 0) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(debugROB = enable)
+      core = tp.tileParams.core.copy(debugROB = Some(DebugROBParams(size)))
     ))
   }
 })

diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala
@@ -727,7 +727,9 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
   val io = IO(new FPUIO)
 
   val (useClockGating, useDebugROB) = coreParams match {
-    case r: RocketCoreParams => (r.clockGate, r.debugROB)
+    case r: RocketCoreParams =>
+      val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
+      (r.clockGate, sz < 1)
     case _ => (false, false)
   }
   val clock_en_reg = Reg(Bool())