Popular repositories Loading

1. pipeline_IITB_RISC pipeline_IITB_RISC Public

   The project is 5 stage pipline CPU design of custom RISC ISA.

   Verilog 1

2. rtos_project rtos_project Public

   RTOS sp22 project

   C 1

3. recurrent_feedforward_model recurrent_feedforward_model Public

   Python 1

4. Prosthesis Prosthesis Public

   Python

5. multicycle_IITB_RISC multicycle_IITB_RISC Public

   CPU design in verilog for custom RISC ISA.

   Verilog

6. digital_clock digital_clock Public

   Verilog