[bot] AutoMerging: merge all upstream's changes:

* https://github.com/coolsnowwolf/lede:
  bcm53xx: build a single device per profile
  ramips: fix mt7621 kernel compilation
  mediatek: configure TUF-AX4200 LAN LEDs
  mediatek: apply stock configuration for WAN-LED
  generic: add hack for MT753x LED configuration
  generic: mt7530: enable PHY configuration using OF

target/linux/generic/hack-5.15/766-net-phy-mediatek-ge-add-LED-configuration-interface.patch

@@ -0,0 +1,72 @@
+From cc225d163b5a4f7a0d1968298bf7927306646a47 Mon Sep 17 00:00:00 2001
+From: David Bauer <[email protected]>
+Date: Fri, 28 Apr 2023 01:53:01 +0200
+Subject: [PATCH] net: phy: mediatek-ge: add LED configuration interface
+
+This adds a small hack similar to the one used for ar8xxx switches to
+read a reg:value map for configuring the LED configuration registers.
+
+This allows OpenWrt to write device-specific LED action as well as blink
+configurations. It is unlikely to be accepted upstream, as upstream
+plans on integrating their own framework for handling these LEDs.
+
+Signed-off-by: David Bauer <[email protected]>
+---
+ drivers/net/phy/mediatek-ge.c | 33 +++++++++++++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+
+--- a/drivers/net/phy/mediatek-ge.c
++++ b/drivers/net/phy/mediatek-ge.c
+@@ -1,4 +1,5 @@
+ // SPDX-License-Identifier: GPL-2.0+
++#include <linux/of.h>
+ #include <linux/bitfield.h>
+ #include <linux/module.h>
+ #include <linux/phy.h>
+@@ -53,6 +54,36 @@ static int mt7530_phy_config_init(struct
+ 	return 0;
+ }
+
++static int mt7530_led_config_of(struct phy_device *phydev)
++{
++	struct device_node *np = phydev->mdio.dev.of_node;
++	const __be32 *paddr;
++	int len;
++	int i;
++
++	paddr = of_get_property(np, "mediatek,led-config", &len);
++	if (!paddr)
++		return 0;
++
++	if (len < (2 * sizeof(*paddr)))
++		return -EINVAL;
++
++	len /= sizeof(*paddr);
++
++	phydev_warn(phydev, "Configure LED registers (num=%d)\n", len);
++	for (i = 0; i < len - 1; i += 2) {
++		u32 reg;
++		u32 val;
++
++		reg = be32_to_cpup(paddr + i);
++		val = be32_to_cpup(paddr + i + 1);
++
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, reg, val);
++	}
++
++	return 0;
++}
++
+ static int mt7531_phy_config_init(struct phy_device *phydev)
+ {
+ 	mtk_gephy_config_init(phydev);
+@@ -65,6 +96,9 @@ static int mt7531_phy_config_init(struct
+ 	phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
+ 	phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
+
++	/* LED Config*/
++	mt7530_led_config_of(phydev);
++
+ 	return 0;
+ }
+

target/linux/generic/pending-5.15/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch

@@ -0,0 +1,43 @@
+From 1d81e51d6d79d9098013b2e8cdd677bae998c5d8 Mon Sep 17 00:00:00 2001
+From: David Bauer <[email protected]>
+Date: Fri, 28 Apr 2023 02:22:59 +0200
+Subject: [PATCH 1/2] mt7530: register OF node for internal MDIO bus
+
+The MT753x switches provide a switch-internal MDIO bus for the embedded
+PHYs.
+
+Register a OF sub-node on the switch OF-node for this internal MDIO bus.
+This allows to configure the embedded PHYs using device-tree.
+
+Signed-off-by: David Bauer <[email protected]>
+---
+ drivers/net/dsa/mt7530.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2081,10 +2081,13 @@ mt7530_setup_mdio(struct mt7530_priv *pr
+ {
+ 	struct dsa_switch *ds = priv->ds;
+ 	struct device *dev = priv->dev;
++	struct device_node *np, *mnp;
+ 	struct mii_bus *bus;
+ 	static int idx;
+ 	int ret;
+
++	np = priv->dev->of_node;
++
+ 	bus = devm_mdiobus_alloc(dev);
+ 	if (!bus)
+ 		return -ENOMEM;
+@@ -2101,7 +2104,9 @@ mt7530_setup_mdio(struct mt7530_priv *pr
+ 	if (priv->irq)
+ 		mt7530_setup_mdio_irq(priv);
+
+-	ret = devm_mdiobus_register(dev, bus);
++	mnp = of_get_child_by_name(np, "mdio");
++	ret = devm_of_mdiobus_register(dev, bus, mnp);
++	of_node_put(mnp);
+ 	if (ret) {
+ 		dev_err(dev, "failed to register MDIO bus: %d\n", ret);
+ 		if (priv->irq)

target/linux/mediatek/dts/mt7986a-asus-tuf-ax4200.dts

@@ -129,7 +129,7 @@
 		reset-deassert-us = <10000>;
 
 		/* LED0: CONN (WAN white) */
-		mxl,led-config = <0x00f0 0x0 0x0 0x0>;
+		mxl,led-config = <0x03f0 0x0 0x0 0x0>;
 	};
 
 	switch: switch@0 {
@@ -267,6 +267,67 @@
 			};
 		};
 	};
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy@1 {
+			reg = <1>;
+
+			mediatek,led-config = <
+				0x21 0x8009 /* BASIC_CTRL */
+				0x22 0x0c00 /* ON_DURATION */
+				0x23 0x1400 /* BLINK_DURATION */
+				0x24 0x8000 /* LED0_ON_CTRL */
+				0x25 0x0000 /* LED0_BLINK_CTRL */
+				0x26 0xc007 /* LED1_ON_CTRL */
+				0x27 0x003f /* LED1_BLINK_CTRL */
+			>;
+		};
+
+		phy@2 {
+			reg = <2>;
+
+			mediatek,led-config = <
+				0x21 0x8009 /* BASIC_CTRL */
+				0x22 0x0c00 /* ON_DURATION */
+				0x23 0x1400 /* BLINK_DURATION */
+				0x24 0x8000 /* LED0_ON_CTRL */
+				0x25 0x0000 /* LED0_BLINK_CTRL */
+				0x26 0xc007 /* LED1_ON_CTRL */
+				0x27 0x003f /* LED1_BLINK_CTRL */
+			>;
+		};
+
+		phy@3 {
+			reg = <3>;
+
+			mediatek,led-config = <
+				0x21 0x8009 /* BASIC_CTRL */
+				0x22 0x0c00 /* ON_DURATION */
+				0x23 0x1400 /* BLINK_DURATION */
+				0x24 0x8000 /* LED0_ON_CTRL */
+				0x25 0x0000 /* LED0_BLINK_CTRL */
+				0x26 0xc007 /* LED1_ON_CTRL */
+				0x27 0x003f /* LED1_BLINK_CTRL */
+			>;
+		};
+
+		phy@4 {
+			reg = <4>;
+
+			mediatek,led-config = <
+				0x21 0x8009 /* BASIC_CTRL */
+				0x22 0x0c00 /* ON_DURATION */
+				0x23 0x1400 /* BLINK_DURATION */
+				0x24 0x8000 /* LED0_ON_CTRL */
+				0x25 0x0000 /* LED0_BLINK_CTRL */
+				0x26 0xc007 /* LED1_ON_CTRL */
+				0x27 0x003f /* LED1_BLINK_CTRL */
+			>;
+		};
+	};
 };
 
 &wmac {

target/linux/mediatek/patches-5.15/730-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch

@@ -55,8 +55,8 @@ Signed-off-by: Daniel Golle <[email protected]>
  	help
 --- a/drivers/net/phy/mediatek-ge.c
 +++ b/drivers/net/phy/mediatek-ge.c
-@@ -1,6 +1,9 @@
- // SPDX-License-Identifier: GPL-2.0+
+@@ -2,6 +2,9 @@
+ #include <linux/of.h>
  #include <linux/bitfield.h>
  #include <linux/module.h>
 +#include <linux/nvmem-consumer.h>
@@ -65,7 +65,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  #include <linux/phy.h>
 
  #define MTK_EXT_PAGE_ACCESS		0x1f
-@@ -11,6 +14,275 @@
+@@ -12,6 +15,275 @@
  #define MTK_PHY_PAGE_EXTENDED_2A30	0x2a30
  #define MTK_PHY_PAGE_EXTENDED_52B5	0x52b5
 
@@ -341,7 +341,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  static int mtk_gephy_read_page(struct phy_device *phydev)
  {
  	return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
-@@ -68,6 +340,1059 @@ static int mt7531_phy_config_init(struct
+@@ -102,6 +374,1059 @@ static int mt7531_phy_config_init(struct
  	return 0;
  }
 
@@ -1401,7 +1401,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  static struct phy_driver mtk_gephy_driver[] = {
  	{
  		PHY_ID_MATCH_EXACT(0x03a29412),
-@@ -97,6 +1422,30 @@ static struct phy_driver mtk_gephy_drive
+@@ -131,6 +1456,30 @@ static struct phy_driver mtk_gephy_drive
  		.read_page	= mtk_gephy_read_page,
  		.write_page	= mtk_gephy_write_page,
  	},
@@ -1432,7 +1432,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  };
 
  module_phy_driver(mtk_gephy_driver);
-@@ -107,6 +1456,8 @@ static struct mdio_device_id __maybe_unu
+@@ -141,6 +1490,8 @@ static struct mdio_device_id __maybe_unu
  };
 
  MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver");