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fuzzgen: Enable SIMD fuzzing for RISC-V (#6949)
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,21 @@ | ||
use cranelift::prelude::isa::TargetIsa; | ||
use target_lexicon::Architecture; | ||
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pub trait TargetIsaExtras { | ||
fn supports_simd(&self) -> bool; | ||
} | ||
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impl TargetIsaExtras for &dyn TargetIsa { | ||
fn supports_simd(&self) -> bool { | ||
match self.triple().architecture { | ||
// RISC-V only supports SIMD with the V extension. | ||
Architecture::Riscv64(_) => self | ||
.isa_flags() | ||
.iter() | ||
.find(|f| f.name == "has_v") | ||
.and_then(|f| f.as_bool()) | ||
.unwrap_or(false), | ||
_ => true, | ||
} | ||
} | ||
} |
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