x64: Use 4 register Vex Inst

cranelift/codegen/src/isa/x64/inst.isle

@@ -195,8 +195,9 @@
 
        ;; XMM (scalar or vector) binary op that relies on the VEX prefix.
        (XmmRmRVex (op AvxOpcode)
-                   (src1 XmmMem)
+                   (src1 Xmm)
                    (src2 Xmm)
+                   (src3 XmmMem)
                    (dst WritableXmm))
 
        ;; XMM (scalar or vector) binary op that relies on the EVEX prefix.
@@ -2815,21 +2816,27 @@
             (_ Unit (emit (MInst.XmmRmR (SseOpcode.Maxpd) x y dst))))
         dst))
 
+
+;; Helper for creating `MInst.XmmRmRVex` instructions.
+(decl xmm_rmr_vex (AvxOpcode Xmm Xmm XmmMem) Xmm)
+(rule (xmm_rmr_vex op src1 src2 src3)
+      (let ((dst WritableXmm (temp_writable_xmm))
+            (_ Unit (emit (MInst.XmmRmRVex op
+                                           src1
+                                           src2
+                                           src3
+                                           dst))))
+        dst))
+
 ;; Helper for creating `vfmadd213ps` instructions.
 (decl x64_vfmadd213ps (Xmm Xmm XmmMem) Xmm)
 (rule (x64_vfmadd213ps x y z)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_1 Unit (emit (MInst.XmmUnaryRmR (SseOpcode.Movups) x dst)))
-            (_2 Unit (emit (MInst.XmmRmRVex (AvxOpcode.Vfmadd213ps) z y dst))))
-        dst))
+      (xmm_rmr_vex (AvxOpcode.Vfmadd213ps) x y z))
 
 ;; Helper for creating `vfmadd213pd` instructions.
 (decl x64_vfmadd213pd (Xmm Xmm XmmMem) Xmm)
 (rule (x64_vfmadd213pd x y z)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_1 Unit (emit (MInst.XmmUnaryRmR (SseOpcode.Movups) x dst)))
-            (_2 Unit (emit (MInst.XmmRmRVex (AvxOpcode.Vfmadd213pd) z y dst))))
-        dst))
+      (xmm_rmr_vex (AvxOpcode.Vfmadd213pd) x y z))
 
 
 ;; Helper for creating `sqrtss` instructions.

cranelift/codegen/src/isa/x64/inst/emit.rs

@@ -1695,18 +1695,21 @@ pub(crate) fn emit(
             op,
             src1,
             src2,
+            src3,
             dst,
         } => {
+            let src1 = allocs.next(src1.to_reg());
             let dst = allocs.next(dst.to_reg().to_reg());
+            debug_assert_eq!(src1, dst);
             let src2 = allocs.next(src2.to_reg());
-            let src1 = src1.clone().to_reg_mem().with_allocs(allocs);
+            let src3 = src3.clone().to_reg_mem().with_allocs(allocs);
 
             let (w, opcode) = match op {
                 AvxOpcode::Vfmadd213ps => (false, 0xA8),
                 AvxOpcode::Vfmadd213pd => (true, 0xA8),
             };
 
-            match src1 {
+            match src3 {
                 RegMem::Reg { reg: src } => VexInstruction::new()
                     .length(VexVectorLength::V128)
                     .prefix(LegacyPrefixes::_66)

cranelift/codegen/src/isa/x64/inst/emit_tests.rs

@@ -3707,13 +3707,13 @@ fn test_x64_emit() {
     insns.push((
         Inst::xmm_rm_r_vex(AvxOpcode::Vfmadd213ps, RegMem::reg(xmm2), xmm1, w_xmm0),
         "C4E271A8C2",
-        "vfmadd213ps %xmm2, %xmm1, %xmm0",
+        "vfmadd213ps %xmm0, %xmm1, %xmm2, %xmm0",
     ));
 
     insns.push((
         Inst::xmm_rm_r_vex(AvxOpcode::Vfmadd213pd, RegMem::reg(xmm5), xmm4, w_xmm3),
         "C4E2D9A8DD",
-        "vfmadd213pd %xmm5, %xmm4, %xmm3",
+        "vfmadd213pd %xmm3, %xmm4, %xmm5, %xmm3",
     ));
 
     // ========================================================

cranelift/codegen/src/isa/x64/inst/mod.rs

@@ -319,14 +319,15 @@ impl Inst {
     }
 
     #[cfg(test)]
-    pub(crate) fn xmm_rm_r_vex(op: AvxOpcode, src1: RegMem, src2: Reg, dst: Writable<Reg>) -> Self {
-        src1.assert_regclass_is(RegClass::Float);
+    pub(crate) fn xmm_rm_r_vex(op: AvxOpcode, src3: RegMem, src2: Reg, dst: Writable<Reg>) -> Self {
+        src3.assert_regclass_is(RegClass::Float);
         debug_assert!(src2.class() == RegClass::Float);
         debug_assert!(dst.to_reg().class() == RegClass::Float);
         Inst::XmmRmRVex {
             op,
-            src1: XmmMem::new(src1).unwrap(),
+            src3: XmmMem::new(src3).unwrap(),
             src2: Xmm::new(src2).unwrap(),
+            src1: Xmm::new(dst.to_reg()).unwrap(),
             dst: WritableXmm::from_writable_reg(dst).unwrap(),
         }
     }
@@ -1147,13 +1148,23 @@ impl PrettyPrint for Inst {
                 op,
                 src1,
                 src2,
+                src3,
                 dst,
                 ..
             } => {
+                let src3 = src3.pretty_print(8, allocs);
                 let src2 = pretty_print_reg(src2.to_reg(), 8, allocs);
+                let src1 = pretty_print_reg(src1.to_reg(), 8, allocs);
                 let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
-                let src1 = src1.pretty_print(8, allocs);
-                format!("{} {}, {}, {}", ljustify(op.to_string()), src1, src2, dst)
+
+                format!(
+                    "{} {}, {}, {}, {}",
+                    ljustify(op.to_string()),
+                    src1,
+                    src2,
+                    src3,
+                    dst
+                )
             }
 
             Inst::XmmRmREvex {
@@ -1864,6 +1875,7 @@ fn x64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandCol
             op,
             src1,
             src2,
+            src3,
             dst,
             ..
         } => {
@@ -1872,10 +1884,10 @@ fn x64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandCol
             // register uses.
             assert!(*op == AvxOpcode::Vfmadd213ps || *op == AvxOpcode::Vfmadd213pd);
 
-            // We both use and def dst
-            collector.reg_mod(dst.to_writable_reg());
+            collector.reg_use(src1.to_reg());
+            collector.reg_reuse_def(dst.to_writable_reg(), 0);
             collector.reg_use(src2.to_reg());
-            src1.get_operands(collector);
+            src3.get_operands(collector);
         }
         Inst::XmmRmREvex {
             op,