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Update to latest BlackParrot #33

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merged 2 commits into from
Oct 21, 2023
Merged

Update to latest BlackParrot #33

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1f1cfe5
Minor updates
dpetrisko Oct 9, 2023
66c7a95
Minor fixes for axi
dpetrisko Oct 21, 2023
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4 changes: 2 additions & 2 deletions axi/v/bp_axi_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ module bp_axi_top
, parameter `BSG_INV_PARAM(axi_size_width_p)
, localparam axi_mask_width_lp = axi_data_width_p>>3

`declare_bp_bedrock_mem_if_widths(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p)
`declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p)
)
(input clk_i
, input reset_i
Expand Down Expand Up @@ -131,7 +131,7 @@ module bp_axi_top
, input [1:0] m_axi_rresp_i
);

`declare_bp_bedrock_mem_if(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p);
`declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p);

bp_bedrock_mem_fwd_header_s mem_fwd_header_li;
logic [bedrock_fill_width_p-1:0] mem_fwd_data_li;
Expand Down
12 changes: 6 additions & 6 deletions axi/v/bp_me_axil_client.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ module bp_me_axil_client
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_default_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_bedrock_mem_if_widths(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p)
`declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p)

// AXI CHANNEL PARAMS
, parameter `BSG_INV_PARAM(axil_data_width_p)
Expand Down Expand Up @@ -65,7 +65,7 @@ module bp_me_axil_client
);

// declaring i/o command and response struct type and size
`declare_bp_bedrock_mem_if(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p);
`declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p);
`bp_cast_o(bp_bedrock_mem_fwd_header_s, mem_fwd_header);
`bp_cast_i(bp_bedrock_mem_rev_header_s, mem_rev_header);

Expand Down Expand Up @@ -103,10 +103,10 @@ module bp_me_axil_client
begin
mem_fwd_data_o = wdata_lo;
mem_fwd_header_cast_o = '0;
mem_fwd_header_cast_o.payload.lce_id = lce_id_i;
mem_fwd_header_cast_o.payload.did = did_i;
mem_fwd_header_cast_o.addr = addr_lo;
mem_fwd_header_cast_o.msg_type = w_lo ? e_bedrock_mem_uc_wr : e_bedrock_mem_uc_rd;
mem_fwd_header_cast_o.payload.lce_id = lce_id_i;
mem_fwd_header_cast_o.payload.src_did = did_i;
mem_fwd_header_cast_o.addr = addr_lo;
mem_fwd_header_cast_o.msg_type = w_lo ? e_bedrock_mem_uc_wr : e_bedrock_mem_uc_rd;
if (~w_lo) begin
// reads are full width
mem_fwd_header_cast_o.size = bp_bedrock_msg_size_e'(lg_axil_mask_width_lp);
Expand Down
14 changes: 7 additions & 7 deletions axi/v/bp_me_axil_master.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ module bp_me_axil_master
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_default_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_bedrock_mem_if_widths(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p)
`declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p)

// AXI WRITE DATA CHANNEL PARAMS
, parameter `BSG_INV_PARAM(axil_data_width_p)
Expand Down Expand Up @@ -65,7 +65,7 @@ module bp_me_axil_master
);

// declaring i/o command and response struct type and size
`declare_bp_bedrock_mem_if(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p);
`declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p);
`bp_cast_i(bp_bedrock_mem_fwd_header_s, mem_fwd_header);
`bp_cast_o(bp_bedrock_mem_rev_header_s, mem_rev_header);

Expand Down Expand Up @@ -119,7 +119,7 @@ module bp_me_axil_master
,.ready_o(stream_fifo_ready_and_lo)

,.data_o(fsm_rev_header_li)
,.v_o(stream_header_v_lo)
,.v_o()
,.yumi_i(fsm_rev_ready_and_lo & fsm_rev_v_li & fsm_rev_last_lo)
);

Expand Down Expand Up @@ -189,11 +189,11 @@ module bp_me_axil_master
,.data_o(fsm_rev_data_li)
);

logic v_lo, yumi_li;
logic v_lo, ready_and_li;
always_comb
begin
fsm_rev_v_li = stream_header_v_lo & v_lo;
yumi_li = fsm_rev_ready_and_lo & fsm_rev_v_li;
fsm_rev_v_li = v_lo;
ready_and_li = fsm_rev_ready_and_lo;
end

bsg_axil_fifo_master
Expand All @@ -213,7 +213,7 @@ module bp_me_axil_master

,.data_o(rdata_lo)
,.v_o(v_lo)
,.ready_and_i(yumi_li)
,.ready_and_i(ready_and_li)

,.*
);
Expand Down