Update to latest BlackParrot (#33)

* Minor updates * Minor fixes for axi
black-parrot-hdk · Oct 21, 2023 · d4d21c2 · d4d21c2
1 parent f5b0841
commit d4d21c2
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Showing 3 changed files with 15 additions and 15 deletions.
diff --git a/axi/v/bp_axi_top.sv b/axi/v/bp_axi_top.sv
@@ -30,7 +30,7 @@ module bp_axi_top
    , parameter `BSG_INV_PARAM(axi_size_width_p)
    , localparam axi_mask_width_lp = axi_data_width_p>>3
 
-   `declare_bp_bedrock_mem_if_widths(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p)
+   `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p)
    )
   (input                                       clk_i
    , input                                     reset_i
@@ -131,7 +131,7 @@ module bp_axi_top
    , input [1:0]                               m_axi_rresp_i
    );
 
-  `declare_bp_bedrock_mem_if(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p);
+  `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p);
 
   bp_bedrock_mem_fwd_header_s mem_fwd_header_li;
   logic [bedrock_fill_width_p-1:0] mem_fwd_data_li;

diff --git a/axi/v/bp_me_axil_client.sv b/axi/v/bp_me_axil_client.sv
@@ -7,7 +7,7 @@ module bp_me_axil_client
  import bp_me_pkg::*;
  #(parameter bp_params_e bp_params_p = e_bp_default_cfg
   `declare_bp_proc_params(bp_params_p)
-  `declare_bp_bedrock_mem_if_widths(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p)
+  `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p)
 
   // AXI CHANNEL PARAMS
   , parameter `BSG_INV_PARAM(axil_data_width_p)
@@ -65,7 +65,7 @@ module bp_me_axil_client
    );
 
   // declaring i/o command and response struct type and size
-  `declare_bp_bedrock_mem_if(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p);
+  `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p);
   `bp_cast_o(bp_bedrock_mem_fwd_header_s, mem_fwd_header);
   `bp_cast_i(bp_bedrock_mem_rev_header_s, mem_rev_header);
 
@@ -103,10 +103,10 @@ module bp_me_axil_client
     begin
       mem_fwd_data_o = wdata_lo;
       mem_fwd_header_cast_o = '0;
-      mem_fwd_header_cast_o.payload.lce_id = lce_id_i;
-      mem_fwd_header_cast_o.payload.did    = did_i;
-      mem_fwd_header_cast_o.addr           = addr_lo;
-      mem_fwd_header_cast_o.msg_type       = w_lo ? e_bedrock_mem_uc_wr : e_bedrock_mem_uc_rd;
+      mem_fwd_header_cast_o.payload.lce_id  = lce_id_i;
+      mem_fwd_header_cast_o.payload.src_did = did_i;
+      mem_fwd_header_cast_o.addr            = addr_lo;
+      mem_fwd_header_cast_o.msg_type        = w_lo ? e_bedrock_mem_uc_wr : e_bedrock_mem_uc_rd;
       if (~w_lo) begin
         // reads are full width
         mem_fwd_header_cast_o.size = bp_bedrock_msg_size_e'(lg_axil_mask_width_lp);

diff --git a/axi/v/bp_me_axil_master.sv b/axi/v/bp_me_axil_master.sv
@@ -11,7 +11,7 @@ module bp_me_axil_master
  import bp_me_pkg::*;
  #(parameter bp_params_e bp_params_p = e_bp_default_cfg
   `declare_bp_proc_params(bp_params_p)
-  `declare_bp_bedrock_mem_if_widths(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p)
+  `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p)
 
   // AXI WRITE DATA CHANNEL PARAMS
   , parameter `BSG_INV_PARAM(axil_data_width_p)
@@ -65,7 +65,7 @@ module bp_me_axil_master
   );
 
   // declaring i/o command and response struct type and size
-  `declare_bp_bedrock_mem_if(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p);
+  `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p);
   `bp_cast_i(bp_bedrock_mem_fwd_header_s, mem_fwd_header);
   `bp_cast_o(bp_bedrock_mem_rev_header_s, mem_rev_header);
 
@@ -119,7 +119,7 @@ module bp_me_axil_master
      ,.ready_o(stream_fifo_ready_and_lo)
 
      ,.data_o(fsm_rev_header_li)
-     ,.v_o(stream_header_v_lo)
+     ,.v_o()
      ,.yumi_i(fsm_rev_ready_and_lo & fsm_rev_v_li & fsm_rev_last_lo)
      );
 
@@ -189,11 +189,11 @@ module bp_me_axil_master
      ,.data_o(fsm_rev_data_li)
      );
 
-  logic v_lo, yumi_li;
+  logic v_lo, ready_and_li;
   always_comb
     begin
-      fsm_rev_v_li = stream_header_v_lo & v_lo;
-      yumi_li = fsm_rev_ready_and_lo & fsm_rev_v_li;
+      fsm_rev_v_li = v_lo;
+      ready_and_li = fsm_rev_ready_and_lo;
     end
 
   bsg_axil_fifo_master
@@ -213,7 +213,7 @@ module bp_me_axil_master
 
      ,.data_o(rdata_lo)
      ,.v_o(v_lo)
-     ,.ready_and_i(yumi_li)
+     ,.ready_and_i(ready_and_li)
 
      ,.*
      );