Minor fixes for BlackParrot

black-parrot-hdk · Nov 11, 2023 · 77c78d2 · 77c78d2
1 parent ac40dd6
commit 77c78d2
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Showing 8 changed files with 49 additions and 49 deletions.
diff --git a/axi/v/bp_axi_top.sv b/axi/v/bp_axi_top.sv
@@ -148,12 +148,12 @@ module bp_axi_top
 
   // DMA interface from BP to cache2axi
   `declare_bsg_cache_dma_pkt_s(daddr_width_p, l2_block_size_in_words_p);
-  bsg_cache_dma_pkt_s [num_cce_p*l2_banks_p-1:0] dma_pkt_lo;
-  logic [num_cce_p*l2_banks_p-1:0] dma_pkt_v_lo, dma_pkt_ready_and_li;
-  logic [num_cce_p*l2_banks_p-1:0][l2_fill_width_p-1:0] dma_data_lo;
-  logic [num_cce_p*l2_banks_p-1:0] dma_data_v_lo, dma_data_ready_and_li;
-  logic [num_cce_p*l2_banks_p-1:0][l2_fill_width_p-1:0] dma_data_li;
-  logic [num_cce_p*l2_banks_p-1:0] dma_data_v_li, dma_data_ready_and_lo;
+  bsg_cache_dma_pkt_s [num_cce_p*l2_dmas_p-1:0] dma_pkt_lo;
+  logic [num_cce_p*l2_dmas_p-1:0] dma_pkt_v_lo, dma_pkt_ready_and_li;
+  logic [num_cce_p*l2_dmas_p-1:0][l2_fill_width_p-1:0] dma_data_lo;
+  logic [num_cce_p*l2_dmas_p-1:0] dma_data_v_lo, dma_data_ready_and_li;
+  logic [num_cce_p*l2_dmas_p-1:0][l2_fill_width_p-1:0] dma_data_li;
+  logic [num_cce_p*l2_dmas_p-1:0] dma_data_v_li, dma_data_ready_and_lo;
 
   bp_processor
    #(.bp_params_p(bp_params_p))
@@ -250,11 +250,11 @@ module bp_axi_top
 
   // If necessary, downsize to axi data width. This could be done in bsg_cache_to_axi,
   //   but punt for now
-  logic [num_cce_p*l2_banks_p-1:0][axi_data_width_p-1:0] axi_dma_data_lo;
-  logic [num_cce_p*l2_banks_p-1:0] axi_dma_data_v_lo, axi_dma_data_ready_and_li;
-  logic [num_cce_p*l2_banks_p-1:0][axi_data_width_p-1:0] axi_dma_data_li;
-  logic [num_cce_p*l2_banks_p-1:0] axi_dma_data_v_li, axi_dma_data_yumi_lo;
-  for (genvar i = 0; i < num_cce_p*l2_banks_p; i++)
+  logic [num_cce_p*l2_dmas_p-1:0][axi_data_width_p-1:0] axi_dma_data_lo;
+  logic [num_cce_p*l2_dmas_p-1:0] axi_dma_data_v_lo, axi_dma_data_ready_and_li;
+  logic [num_cce_p*l2_dmas_p-1:0][axi_data_width_p-1:0] axi_dma_data_li;
+  logic [num_cce_p*l2_dmas_p-1:0] axi_dma_data_v_li, axi_dma_data_yumi_lo;
+  for (genvar i = 0; i < num_cce_p*l2_dmas_p; i++)
     begin : narrow
       bsg_serial_in_parallel_out_full
        #(.width_p(axi_data_width_p), .els_p(l2_fill_width_p/axi_data_width_p))
@@ -292,11 +292,12 @@ module bp_axi_top
      ,.data_width_p(axi_data_width_p)
      ,.mask_width_p(l2_block_size_in_words_p)
      ,.block_size_in_words_p(l2_block_width_p/axi_data_width_p)
-     ,.num_cache_p(num_cce_p*l2_banks_p)
+     ,.num_cache_p(num_cce_p*l2_dmas_p)
      ,.axi_data_width_p(axi_data_width_p)
      ,.axi_id_width_p(axi_id_width_p)
      ,.axi_burst_len_p(l2_block_width_p/axi_data_width_p)
      ,.axi_burst_type_p(e_axi_burst_incr)
+     ,.ordering_en_p(1)
      )
    cache2axi
     (.clk_i(clk_i)

diff --git a/manycore/v/bp_me_manycore_bridge.sv b/manycore/v/bp_me_manycore_bridge.sv
@@ -7,7 +7,7 @@ module bp_me_manycore_bridge
  import bp_me_pkg::*;
  #(parameter bp_params_e bp_params_p = e_bp_default_cfg
    `declare_bp_proc_params(bp_params_p)
-   `declare_bp_bedrock_mem_if_widths(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p)
+   `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p)
 
    , parameter `BSG_INV_PARAM(x_cord_width_p)
    , parameter `BSG_INV_PARAM(y_cord_width_p)

diff --git a/manycore/v/bp_me_manycore_dram.sv b/manycore/v/bp_me_manycore_dram.sv
@@ -7,7 +7,7 @@ module bp_me_manycore_dram
  import bsg_manycore_pkg::*;
  #(parameter bp_params_e bp_params_p = e_bp_default_cfg
    `declare_bp_proc_params(bp_params_p)
-   `declare_bp_bedrock_mem_if_widths(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p)
+   `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p)
 
    , parameter `BSG_INV_PARAM(x_cord_width_p)
    , parameter `BSG_INV_PARAM(pod_x_cord_width_p)
@@ -53,7 +53,7 @@ module bp_me_manycore_dram
    , input [addr_width_p-1:0]                   dram_offset_i
    );
 
-  `declare_bp_bedrock_mem_if(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p);
+  `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p)
   `declare_bp_memory_map(paddr_width_p, daddr_width_p);
   `declare_bsg_manycore_packet_s(addr_width_p, data_width_p, x_cord_width_p, y_cord_width_p);
   `bp_cast_i(bp_bedrock_mem_fwd_header_s, mem_fwd_header);

diff --git a/manycore/v/bp_me_manycore_fifo.sv b/manycore/v/bp_me_manycore_fifo.sv
@@ -8,7 +8,7 @@ module bp_me_manycore_fifo
  import bsg_manycore_pkg::*;
  #(parameter bp_params_e bp_params_p = e_bp_default_cfg
    `declare_bp_proc_params(bp_params_p)
-   `declare_bp_bedrock_mem_if_widths(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p)
+   `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p)
 
    , parameter `BSG_INV_PARAM(x_cord_width_p)
    , parameter `BSG_INV_PARAM(y_cord_width_p)
@@ -38,7 +38,7 @@ module bp_me_manycore_fifo
    , input [y_cord_width_p-1:0]                 global_y_i
    );
 
-  `declare_bp_bedrock_mem_if(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p);
+  `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p);
   `declare_bp_memory_map(paddr_width_p, daddr_width_p);
 
   localparam x_cord_width_pad_lp = `BSG_CDIV(x_cord_width_p, 8) * 8;

diff --git a/manycore/v/bp_me_manycore_mmio.sv b/manycore/v/bp_me_manycore_mmio.sv
@@ -7,7 +7,7 @@ module bp_me_manycore_mmio
  import bsg_manycore_pkg::*;
  #(parameter bp_params_e bp_params_p = e_bp_default_cfg
    `declare_bp_proc_params(bp_params_p)
-   `declare_bp_bedrock_mem_if_widths(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p)
+   `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p)
 
    , parameter `BSG_INV_PARAM(x_cord_width_p)
    , parameter `BSG_INV_PARAM(pod_x_cord_width_p)
@@ -64,7 +64,7 @@ module bp_me_manycore_mmio
    , input [y_cord_width_p-1:0]                 global_y_i
    );
 
-  `declare_bp_bedrock_mem_if(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p);
+  `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p);
   `declare_bp_memory_map(paddr_width_p, daddr_width_p);
   `declare_bsg_manycore_packet_s(addr_width_p, data_width_p, x_cord_width_p, y_cord_width_p);
   `bp_cast_i(bp_bedrock_mem_fwd_header_s, mem_fwd_header);
@@ -336,9 +336,9 @@ module bp_me_manycore_mmio
     begin
       mem_fwd_header_cast_o = '0;
       mem_fwd_header_cast_o.payload.lce_id = 2'b10; // Always 2'b10 for I/O
-      mem_fwd_header_cast_o.payload.did[0+:x_cord_width_p] = packet_lo.src_x_cord;
-      mem_fwd_header_cast_o.payload.did[x_cord_width_p+:y_cord_width_p] = packet_lo.src_y_cord;
-      mem_fwd_header_cast_o.payload.did[x_cord_width_p+y_cord_width_p+:5] = packet_lo.reg_id;
+      mem_fwd_header_cast_o.payload.src_did[0+:x_cord_width_p] = packet_lo.src_x_cord;
+      mem_fwd_header_cast_o.payload.src_did[x_cord_width_p+:y_cord_width_p] = packet_lo.src_y_cord;
+      mem_fwd_header_cast_o.payload.src_did[x_cord_width_p+y_cord_width_p+:5] = packet_lo.reg_id;
       mem_fwd_header_cast_o.msg_type = (packet_lo.op_v2 inside {e_remote_load}) ? e_bedrock_mem_uc_rd : e_bedrock_mem_uc_wr;
       // TODO: we only support 32-bit loads and stores to BP configuration addresses
       mem_fwd_header_cast_o.size = e_bedrock_msg_size_4;
@@ -371,9 +371,9 @@ module bp_me_manycore_mmio
       // TODO: Handle subword ops, float / ifetch ops
       return_packet_li.pkt_type = (mem_rev_header_cast_i.msg_type inside {e_bedrock_mem_uc_wr}) ? e_return_credit : e_return_int_wb;
       return_packet_li.data = mem_rev_data_i;
-      return_packet_li.x_cord = mem_rev_header_cast_i.payload.did[0+:x_cord_width_p];
-      return_packet_li.y_cord = mem_rev_header_cast_i.payload.did[x_cord_width_p+:y_cord_width_p];
-      return_packet_li.reg_id = mem_rev_header_cast_i.payload.did[x_cord_width_p+y_cord_width_p+:5];
+      return_packet_li.x_cord = mem_rev_header_cast_i.payload.src_did[0+:x_cord_width_p];
+      return_packet_li.y_cord = mem_rev_header_cast_i.payload.src_did[x_cord_width_p+:y_cord_width_p];
+      return_packet_li.reg_id = mem_rev_header_cast_i.payload.src_did[x_cord_width_p+y_cord_width_p+:5];
     end
 
 endmodule

diff --git a/manycore/v/bsg_manycore_switch_1x2.sv b/manycore/v/bsg_manycore_switch_1x2.sv
@@ -51,18 +51,14 @@ module bsg_manycore_switch_1x2
   wire is_sready = (send_state_r == e_sready);
   wire is_send0  = (send_state_r == e_send0);
   wire is_send1  = (send_state_r == e_send1);
-  bsg_manycore_packet_s fwd_packet;
-  assign fwd_packet = multi_fwd_link_sif_cast_i.data;
-  wire [addr_width_p-1:0] fwd_epa = (fwd_packet.addr << 2) | (fwd_packet.payload.load_info_s.load_info.part_sel);
-  wire fwd_select = (fwd_epa >= split_addr_p);
 
   assign fwd_link_sif_cast_o[0].data             = multi_fwd_link_sif_cast_i.data;
-  assign fwd_link_sif_cast_o[0].v                = multi_fwd_link_sif_cast_i.v & !fwd_select;
+  assign fwd_link_sif_cast_o[0].v                = multi_fwd_link_sif_cast_i.v & is_send0;
   assign fwd_link_sif_cast_o[1].data             = multi_fwd_link_sif_cast_i.data;
-  assign fwd_link_sif_cast_o[1].v                = multi_fwd_link_sif_cast_i.v &  fwd_select;
+  assign fwd_link_sif_cast_o[1].v                = multi_fwd_link_sif_cast_i.v & is_send1;
   assign multi_fwd_link_sif_cast_o.ready_and_rev =
-    (fwd_link_sif_cast_o[0].v & fwd_link_sif_cast_i[0].ready_and_rev)
-    | (fwd_link_sif_cast_o[1].v & fwd_link_sif_cast_i[1].ready_and_rev);
+    (is_send0 & fwd_link_sif_cast_i[0].ready_and_rev)
+    | (is_send1 & fwd_link_sif_cast_i[1].ready_and_rev);
 
   bsg_manycore_return_packet_s multi_rev_data_lo;
   logic multi_rev_tag_lo, multi_rev_v_lo, multi_rev_yumi_li;
@@ -95,21 +91,26 @@ module bsg_manycore_switch_1x2
   // Arbitrary for now
   localparam outstanding_sends_lp = 127;
   logic [`BSG_WIDTH(outstanding_sends_lp)-1:0] send_cnt_lo;
-  bsg_flow_counter
-   #(.els_p(outstanding_sends_lp))
+  bsg_counter_up_down
+   #(.max_val_p(outstanding_sends_lp), .init_val_p(0), .max_step_p(1))
    sfc
     (.clk_i(clk_i)
      ,.reset_i(reset_i)
 
-     ,.v_i(multi_fwd_link_sif_cast_i.v)
-     ,.ready_i(multi_fwd_link_sif_cast_o.ready_and_rev)
-     ,.yumi_i(multi_rev_link_sif_cast_i.ready_and_rev)
+     ,.up_i(multi_fwd_link_sif_cast_o.ready_and_rev & multi_fwd_link_sif_cast_i.v)
+     // Credit-based
+     ,.down_i(multi_rev_link_sif_cast_i.ready_and_rev)
 
      ,.count_o(send_cnt_lo)
      );
 
-  wire send0 = fwd_link_sif_cast_o[0].v & fwd_link_sif_cast_i[0].ready_and_rev;
-  wire send1 = fwd_link_sif_cast_o[1].v & fwd_link_sif_cast_i[1].ready_and_rev;
+  bsg_manycore_packet_s fwd_packet;
+  assign fwd_packet = multi_fwd_link_sif_cast_i.data;
+  wire [1:0] fwd_part_sel = fwd_packet.payload.load_info_s.load_info.part_sel;
+  wire [addr_width_p-1:0] fwd_epa = (fwd_packet.addr << 2) | fwd_part_sel;
+  wire fwd_select = (fwd_epa >= split_addr_p);
+  wire send0 = multi_fwd_link_sif_cast_i.v & !fwd_select;
+  wire send1 = multi_fwd_link_sif_cast_i.v &  fwd_select;
   wire send_drained = (send_cnt_lo == '0) & ~send0 & ~send1;
   always_comb
     unique casez (send_state_r)
@@ -170,15 +171,14 @@ module bsg_manycore_switch_1x2
   // Arbitrary for now
   localparam outstanding_recvs_lp = 127;
   logic [`BSG_WIDTH(outstanding_recvs_lp)-1:0] recv_cnt_lo;
-  bsg_flow_counter
-   #(.els_p(outstanding_recvs_lp))
+  bsg_counter_up_down
+   #(.max_val_p(outstanding_recvs_lp), .init_val_p(0), .max_step_p(1))
    rfc
     (.clk_i(clk_i)
      ,.reset_i(reset_i)
 
-     ,.v_i(multi_fwd_link_sif_cast_o.v)
-     ,.ready_i(multi_fwd_link_sif_cast_i.ready_and_rev)
-     ,.yumi_i(multi_rev_link_sif_cast_i.v & multi_rev_link_sif_cast_o.ready_and_rev)
+     ,.up_i(multi_fwd_link_sif_cast_o.v)
+     ,.down_i(multi_rev_link_sif_cast_o.ready_and_rev & multi_rev_link_sif_cast_i.v)
 
      ,.count_o(recv_cnt_lo)
      );

diff --git a/manycore/v/bsg_manycore_tile_blackparrot.sv b/manycore/v/bsg_manycore_tile_blackparrot.sv
@@ -46,7 +46,7 @@ module bsg_manycore_tile_blackparrot
  import bp_common_pkg::*;
  #(parameter bp_params_e bp_params_p = e_bp_default_cfg
    `declare_bp_proc_params(bp_params_p)
-   `declare_bp_bedrock_mem_if_widths(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p)
+   `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p)
    , parameter `BSG_INV_PARAM(x_cord_width_p)
    , parameter `BSG_INV_PARAM(y_cord_width_p)
    , parameter `BSG_INV_PARAM(pod_x_cord_width_p)
@@ -76,8 +76,8 @@ module bsg_manycore_tile_blackparrot
    );
 
   `declare_bp_memory_map(paddr_width_p, daddr_width_p);
-  `declare_bp_bedrock_mem_if(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p);
-  `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p);
+  `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p);
+  `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p);
   bp_cfg_bus_s cfg_bus_lo; 
 
   localparam num_proc_lp = 3;

diff --git a/manycore/v/bsg_manycore_tile_blackparrot_mesh.sv b/manycore/v/bsg_manycore_tile_blackparrot_mesh.sv
@@ -8,7 +8,6 @@ module bsg_manycore_tile_blackparrot_mesh
  import bsg_noc_pkg::*;
  #(parameter bp_params_e bp_params_p = e_bp_default_cfg
    `declare_bp_proc_params(bp_params_p)
-   `declare_bp_bedrock_mem_if_widths(paddr_width_p, did_width_p, lce_id_width_p, lce_assoc_p)
    , parameter `BSG_INV_PARAM(x_cord_width_p)
    , parameter `BSG_INV_PARAM(y_cord_width_p)
    , parameter `BSG_INV_PARAM(pod_x_cord_width_p)