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Move test control logic to Haskell #536

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merged 4 commits into from
Sep 10, 2024
Merged

Move test control logic to Haskell #536

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77f02b2
Add `vivado-hs`
martijnbastiaan Jun 4, 2024
06b3b08
Vivado-hs: support getting back return values
JvWesterveld Jun 18, 2024
44bf0e4
Move HITL test control logic from Tcl to Haskell
JvWesterveld Aug 22, 2024
8ce4978
Disable fourmolu for table
martijnbastiaan Sep 6, 2024
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26 changes: 13 additions & 13 deletions .github/synthesis/all.json
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Original file line number Diff line number Diff line change
Expand Up @@ -12,17 +12,17 @@
{"top": "switchCalendar1k", "stage": "hdl"},
{"top": "switchCalendar1kReducedPins", "stage": "pnr"},

{"top": "boardTestExtended", "stage": "test", "targets": "All" },
{"top": "boardTestSimple", "stage": "test", "targets": "All" },
{"top": "extraProbesTest", "stage": "test", "targets": "Specific [0]" },
{"top": "fincFdecTests", "stage": "test", "targets": "Specific [-1]"},
{"top": "fullMeshHwCcTest", "stage": "test", "targets": "All" },
{"top": "fullMeshHwCcWithRiscvTest", "stage": "test", "targets": "All" },
{"top": "fullMeshSwCcTest", "stage": "test", "targets": "All" },
{"top": "hwCcTopologyTest", "stage": "test", "targets": "All" },
{"top": "linkConfigurationTest", "stage": "test", "targets": "All" },
{"top": "syncInSyncOut", "stage": "test", "targets": "All" },
{"top": "temperatureMonitor", "stage": "test", "targets": "All" },
{"top": "transceiversUpTest", "stage": "test", "targets": "All" },
{"top": "vexRiscvTest", "stage": "test", "targets": "Specific [-1]"}
{"top": "boardTestExtended", "stage": "test"},
{"top": "boardTestSimple", "stage": "test"},
{"top": "fincFdecTests", "stage": "test"},
{"top": "fullMeshHwCcTest", "stage": "test"},
{"top": "fullMeshHwCcWithRiscvTest", "stage": "test"},
{"top": "fullMeshSwCcTest", "stage": "test"},
{"top": "hwCcTopologyTest", "stage": "test"},
{"top": "linkConfigurationTest", "stage": "test"},
{"top": "safeDffSynchronizer", "stage": "hdl" },
{"top": "syncInSyncOut", "stage": "test"},
{"top": "temperatureMonitor", "stage": "test"},
{"top": "transceiversUpTest", "stage": "test"},
{"top": "vexRiscvTest", "stage": "test"}
]
10 changes: 5 additions & 5 deletions .github/synthesis/staging.json
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@@ -1,8 +1,8 @@
[
{"top": "fullMeshHwCcTest", "stage": "test", "targets": "All"},
{"top": "fullMeshSwCcTest", "stage": "test", "targets": "All"},
{"top": "linkConfigurationTest", "stage": "test", "targets": "All"},
{"top": "fullMeshHwCcTest", "stage": "test"},
{"top": "fullMeshSwCcTest", "stage": "test"},
{"top": "linkConfigurationTest", "stage": "test"},
{"top": "safeDffSynchronizer", "stage": "hdl"},
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{"top": "transceiversUpTest", "stage": "test", "targets": "All"},
{"top": "vexRiscvTest", "stage": "test", "targets": "Specific [-1]"}
{"top": "transceiversUpTest", "stage": "test"},
{"top": "vexRiscvTest", "stage": "test"}
]
4 changes: 2 additions & 2 deletions .github/workflows/ci.yml
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Expand Up @@ -171,7 +171,7 @@ jobs:
./cargo.sh build --frozen --release
export BITTIDE_ARTIFACT_ACCESS_TOKEN="${{ secrets.GITHUB_TOKEN }}"
export RUNREF="${{ github.server_url }}/${{ github.repository }}/actions/runs/${{ github.run_id }}"
cabal run -- bittide-tools:cc-plot ${{ github.run_id }}:hwCcTopologyTest _build/plot hitl-topology-plots
cabal run -- bittide-tools:cc-plot ${{ github.run_id }}:hwCcTopologyTest hitl-topology-plots

- name: Generate clock control reports
run: |
Expand Down Expand Up @@ -641,7 +641,7 @@ jobs:
- name: Run tests on hardware
run: |
.github/scripts/with_vivado.sh \
shake ${{ matrix.target.top }}:test --hardware-targets="${{ matrix.target.targets}}"
shake ${{ matrix.target.top }}:test

- name: Archive ILA data
if: ${{ !cancelled() }}
Expand Down
1 change: 1 addition & 0 deletions bittide-experiments/bittide-experiments.cabal
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Expand Up @@ -76,6 +76,7 @@ common common-options
ghc-typelits-extra,
ghc-typelits-knownnat,
ghc-typelits-natnormalise,
template-haskell,

library
import: common-options
Expand Down
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