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@@ -1 +1 @@ | ||
include $(RIOTBASE)/Makefile.base | ||
include $(RIOTBASE)/Makefile.base |
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@@ -1,3 +1,11 @@ | ||
/* | ||
* Copyright (C) 2017 Koen Zandberg <[email protected]> | ||
* | ||
* This file is subject to the terms and conditions of the GNU Lesser | ||
* General Public License v2.1. See the file LICENSE in the top level | ||
* directory for more details. | ||
*/ | ||
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||
/** | ||
* @ingroup drivers_mrf24j40 | ||
* @{ | ||
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Original file line number | Diff line number | Diff line change |
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@@ -1,3 +1,11 @@ | ||
/* | ||
* Copyright (C) 2017 Koen Zandberg <[email protected]> | ||
* | ||
* This file is subject to the terms and conditions of the GNU Lesser | ||
* General Public License v2.1. See the file LICENSE in the top level | ||
* directory for more details. | ||
*/ | ||
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||
/** | ||
* @ingroup drivers_mrf24j40 | ||
* @{ | ||
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@@ -18,7 +26,7 @@ extern "C" { | |
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/** | ||
* @brief SPI access specifiers | ||
****@{ | ||
*****@{ | ||
*/ | ||
#define MRF24J40_SHORT_ADDR_TRANS (0x00) | ||
#define MRF24J40_LONG_ADDR_TRANS (0x80) | ||
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@@ -30,7 +38,7 @@ extern "C" { | |
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/** | ||
* @brief FIFO-Address-Map | ||
***@{ | ||
****@{ | ||
*/ | ||
#define MRF24J40_TX_NORMAL_FIFO (0x000) | ||
#define MRF24J40_TX_BEACON_FIFO (0x080) | ||
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@@ -41,7 +49,7 @@ extern "C" { | |
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/** | ||
* @brief Short-Register addresses | ||
****@{ | ||
*****@{ | ||
*/ | ||
#define MRF24J40_REG_RXMCR (0x00) | ||
#define MRF24J40_REG_PANIDL (0x01) | ||
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@@ -105,7 +113,7 @@ extern "C" { | |
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/** | ||
* @brief Long-Register addresses | ||
****@{ | ||
*****@{ | ||
*/ | ||
#define MRF24J40_REG_RFCON0 (0x200) | ||
#define MRF24J40_REG_RFCON1 (0x201) | ||
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@@ -436,4 +444,3 @@ extern "C" { | |
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#endif /* MRF24J40_REGISTERS_H */ | ||
/** @} */ | ||
|
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,3 +1,11 @@ | ||
/* | ||
* Copyright (C) 2017 Koen Zandberg <[email protected]> | ||
* | ||
* This file is subject to the terms and conditions of the GNU Lesser | ||
* General Public License v2.1. See the file LICENSE in the top level | ||
* directory for more details. | ||
*/ | ||
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||
/** | ||
* @ingroup drivers_mrf24j40 | ||
* @{ | ||
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@@ -22,6 +30,7 @@ void mrf24j40_init(mrf24j40_t *dev) | |
{ | ||
uint8_t softrst; | ||
uint8_t order; | ||
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mrf24j40_hardware_reset(dev); | ||
/* do a soft reset */ | ||
mrf24j40_reg_write_short(dev, MRF24J40_REG_SOFTRST, 0x7); // from manual | ||
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@@ -38,21 +47,21 @@ void mrf24j40_init(mrf24j40_t *dev) | |
mrf24j40_reg_write_short(dev, MRF24J40_REG_RXFLUSH, MRF24J40_RXFLUSH_RXFLUSH); | ||
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/* Here starts init-process as described on MRF24J40 Manual Chap. 3.2 */ | ||
mrf24j40_reg_write_short(dev, MRF24J40_REG_PACON2, ( MRF24J40_PACON2_TXONTS2 | | ||
MRF24J40_PACON2_TXONTS1 | | ||
MRF24J40_PACON2_FIFOEN) ); | ||
mrf24j40_reg_write_short(dev, MRF24J40_REG_TXSTBL, ( MRF24J40_TXSTBL_RFSTBL3 | | ||
MRF24J40_TXSTBL_RFSTBL0 | | ||
MRF24J40_TXSTBL_MSIFS2 | | ||
MRF24J40_TXSTBL_MSIFS0 )); | ||
mrf24j40_reg_write_short(dev, MRF24J40_REG_PACON2, (MRF24J40_PACON2_TXONTS2 | | ||
MRF24J40_PACON2_TXONTS1 | | ||
MRF24J40_PACON2_FIFOEN)); | ||
mrf24j40_reg_write_short(dev, MRF24J40_REG_TXSTBL, (MRF24J40_TXSTBL_RFSTBL3 | | ||
MRF24J40_TXSTBL_RFSTBL0 | | ||
MRF24J40_TXSTBL_MSIFS2 | | ||
MRF24J40_TXSTBL_MSIFS0)); | ||
mrf24j40_reg_write_long(dev, MRF24J40_REG_RFCON1, MRF24J40_RFCON1_VCOOPT1); | ||
mrf24j40_reg_write_long(dev, MRF24J40_REG_RFCON2, MRF24J40_RFCON2_PLLEN); | ||
mrf24j40_reg_write_long(dev, MRF24J40_REG_RFCON6, ( MRF24J40_RFCON6_TXFIL | | ||
MRF24J40_RFCON6_20MRECVR )); | ||
mrf24j40_reg_write_long(dev, MRF24J40_REG_RFCON6, (MRF24J40_RFCON6_TXFIL | | ||
MRF24J40_RFCON6_20MRECVR)); | ||
mrf24j40_reg_write_long(dev, MRF24J40_REG_RFCON7, MRF24J40_RFCON7_SLPCLKSEL1 ); | ||
mrf24j40_reg_write_long(dev, MRF24J40_REG_RFCON8, MRF24J40_RFCON8_RFVCO ); | ||
mrf24j40_reg_write_long(dev, MRF24J40_REG_SLPCON1, ( MRF24J40_SLPCON1_CLKOUTEN | | ||
MRF24J40_SLPCON1_SLPCLKDIV0 )); | ||
mrf24j40_reg_write_long(dev, MRF24J40_REG_SLPCON1, (MRF24J40_SLPCON1_CLKOUTEN | | ||
MRF24J40_SLPCON1_SLPCLKDIV0)); | ||
mrf24j40_reg_write_short(dev, MRF24J40_REG_BBREG2, MRF25J40_BBREG2_CCAMODE1 ); | ||
mrf24j40_reg_write_short(dev, MRF24J40_REG_CCAEDTH, 0x60); | ||
mrf24j40_reg_write_short(dev, MRF24J40_REG_BBREG6, MRF24J40_BBREG6_RSSIMODE2 ); | ||
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@@ -69,7 +78,7 @@ void mrf24j40_init(mrf24j40_t *dev) | |
mrf24j40_reg_read_short(dev, MRF24J40_REG_INTSTAT); | ||
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/* mrf24j40_set_interrupts */ | ||
mrf24j40_reg_write_short(dev, MRF24J40_REG_INTCON, ~( MRF24J40_INTCON_RXIE | MRF24J40_INTCON_TXNIE )); | ||
mrf24j40_reg_write_short(dev, MRF24J40_REG_INTCON, ~(MRF24J40_INTCON_RXIE | MRF24J40_INTCON_TXNIE)); | ||
//Wait until the RFSTATE machine indicates RX state | ||
} | ||
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@@ -200,18 +209,20 @@ void mrf24j40_reset_tasks(mrf24j40_t *dev) | |
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void mrf24j40_update_tasks(mrf24j40_t *dev) | ||
{ | ||
uint8_t instat = 0; | ||
uint8_t newpending = 0; | ||
if(dev->irq_flag){ | ||
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if (dev->irq_flag) { | ||
uint8_t newpending = 0; | ||
uint8_t instat = 0; | ||
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dev->irq_flag = 0; | ||
instat = mrf24j40_reg_read_short(dev, MRF24J40_REG_INTSTAT); | ||
/* check if TX done */ | ||
if(instat & MRF24J40_INTSTAT_TXNIF){ | ||
newpending |= MRF24J40_TASK_TX_DONE |MRF24J40_TASK_TX_READY; | ||
if (instat & MRF24J40_INTSTAT_TXNIF) { | ||
newpending |= MRF24J40_TASK_TX_DONE | MRF24J40_TASK_TX_READY; | ||
/* transmit done, returning to configured idle state */ | ||
mrf24j40_assert_sleep(dev); | ||
} | ||
if(instat & MRF24J40_INTSTAT_RXIF){ | ||
if (instat & MRF24J40_INTSTAT_RXIF) { | ||
newpending |= MRF24J40_TASK_RX_READY; | ||
} | ||
/* check if RX pending */ | ||
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