Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add RISC-V extension constraints #63

Open
wants to merge 1 commit into
base: main
Choose a base branch
from
Open

Add RISC-V extension constraints #63

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
14 changes: 14 additions & 0 deletions cpu/BUILD
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -153,12 +153,26 @@ constraint_value(
constraint_setting = ":cpu",
)

# Base integer instruction set, 32-bit.
constraint_value(
name = "riscv32",
constraint_setting = ":cpu",
)

# Base integer instruction set, 32-bit, 16 registers.
constraint_value(
name = "riscv32e",
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Is this (and the riscv64e, below) sufficiently different from riscv32 to need a new cpu constraint, or is it better modeled as :riscv32 plus a new extension?

constraint_setting = ":cpu",
)

# Base integer instruction set, 64-bit.
constraint_value(
name = "riscv64",
constraint_setting = ":cpu",
)

# Base integer instruction set, 64-bit, 16 registers.
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Is there any opinion from the riscv expert about what the (inevitable) 64-bit 32-register core will be called? Or, to put it backwards, is the 'e' an official name or is it just what we have been using internally?

constraint_value(
name = "riscv64e",
constraint_setting = ":cpu",
)
Loading