RELEASE V1.4.9

* New functionality: * Improved AFI load times for pipelined accelerator designs. For more details please see [Amazon FPGA image (AFI) pre-fetch and caching features](./hdk/docs/load_times.md). * Ease of Use features: * [Improved SDK Error messaging](./sdk/userspace/fpga_libs/fpga_mgmt/fpga_mgmt.c) * [Improved documentation](./hdk/docs/IPI_GUI_Vivado_Setup.md#switching-between-hdk-and-hlx-flows) to help with transition from [HLX to HDK command line flows](https://forums.aws.amazon.com/thread.jspa?threadID=302718&tstart=0) and vice versa * Incorporates feedback from [aws-fpga Issue 458](#458) by making the ```init_ddr``` function, used in design simulations to initialize DDR, more generic by moving out ATG deselection logic to a new ```deselect_atg_hw``` task * Bug Fixes: * Fixed Shell simulation model (sh_bfm) issue on PCIM AXI read data channel back pressure which was described in HDK 1.4.8 Errata. * Fixed HDK simulation example which [demonstrates DMA and PCIM traffic in parallel](./hdk/cl/examples/cl_dram_dma/verif/tests/test_dma_pcim_concurrent.sv).
aws · Jul 30, 2019 · 6a9e299 · 6a9e299
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diff --git a/ERRATA.md b/ERRATA.md
@@ -8,11 +8,20 @@
 * Multiple SDE instances per CL is not supported in this release.  Support planned for future release.
 * DRAM Data retention is not supported for CL designs with less than 4 DDRs enabled
 * Combinatorial loops in CL designs are not supported.
-* Shell Model (sh_bfm) provided with testbench for design simulations, continues to drive read data on PCIM AXI rdata channel even when rready is de-asserted. Will be fixed in future release.
+* [Automatic Traffic Generator (ATG)](./hdk/cl/examples/cl_dram_dma/design/cl_tst.sv) in SYNC mode does not wait for write response transaction before issuing read transactions. The fix for this issue is planned in a future release.
 
 ## SDK
 
 ## SDAccel (For additional restrictions see [SDAccel ERRATA](./SDAccel/ERRATA.md))
 * Virtual Ethernet is not supported when using SDAccel
 * DRAM Data retention is not supported for kernels that provision less than 4 DDRs
 * Combinatorial loops in CL designs are not supported.
+* When using [Xilinx runtime(XRT) version 2018.3.3.1](https://github.com/Xilinx/XRT/releases/tag/2018.3.3.1) or [AWS FPGA Developer AMI Version 1.6.0](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) your host application could fail with following error:
+
+   ```
+   : symbol lookup error: /opt/xilinx/xrt/lib/libxrt_aws.so: undefined symbol: uuid_parse!
+
+   ```  
+   The SDAccel examples included in the developer kit use a SDAccel configuration file [sdaccel.ini]. To workaround this error please copy the SDAccel configuration file [sdaccel.ini](SDAccel/examples/aws/helloworld_ocl_runtime/sdaccel.ini) to your executable directory and try executing your application again.
+   AWS is working with Xilinx to release a XRT patch to fix this issue.
+
diff --git a/Jenkinsfile b/Jenkinsfile
@@ -505,7 +505,7 @@ if (test_sims) {
                         String xilinx_version = y
                         String cl_name = x
                         String simulator = z
-                        String node_name = "Sim ${cl_name} ${xilinx_version}"
+                        String node_name = "Sim ${cl_name} ${xilinx_version} ${simulator}"
                         String key = "test_${cl_name}__"
                         String report_file = "test_sims_${cl_name}_${xilinx_version}.xml"
                         def tool_module_map = simulator_tool_default_map.get(xilinx_version)

diff --git a/RELEASE_NOTES.md b/RELEASE_NOTES.md
@@ -26,8 +26,30 @@
          *    1 DDR controller implemented in the SH (always available)
          *    3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)
 
+## Release 1.4.9 (See [ERRATA](./ERRATA.md) for unsupported features)
+  * New functionality:
+    * Improved AFI load times for pipelined accelerator designs. For more details please see [Amazon FPGA image (AFI) pre-fetch and caching features](./hdk/docs/load_times.md).
+
+ * Ease of Use features:
+    * [Improved SDK Error messaging](./sdk/userspace/fpga_libs/fpga_mgmt/fpga_mgmt.c)
+    * [Improved documentation](./hdk/docs/IPI_GUI_Vivado_Setup.md#switching-between-hdk-and-hlx-flows) to help with transition from [HLX to HDK command line flows](https://forums.aws.amazon.com/thread.jspa?threadID=302718&tstart=0) and vice versa
+    * Incorporates feedback from [aws-fpga Issue 458](https://github.com/aws/aws-fpga/issues/458) by making the ```init_ddr``` function, used in design simulations to initialize DDR, more generic by moving out ATG deselection logic to a new ```deselect_atg_hw``` task 
+
+ * Bug Fixes:
+    * Fixed Shell simulation model (sh_bfm) issue on PCIM AXI read data channel back pressure which was described in HDK 1.4.8 Errata.
+    * Fixed HDK simulation example which [demonstrates DMA and PCIM traffic in parallel](./hdk/cl/examples/cl_dram_dma/verif/tests/test_dma_pcim_concurrent.sv).
+
+ * Package versions used for validation
+
+   | Package | AMI 1.6.0 [2018.3] |AMI 1.5.0 [2018.2] | AMI 1.4.0 [2017.4] |
+   |---------|------------------------|------------------------|-----------------------|
+   | OS      | Centos 7.6 | Centos 7.5, 7.6 | Centos 7.4 |
+   | kernel  | 3.10.0-957.5.1.el7.x86_64 | 3.10.0-862.11.6.el7.x86_64, 3.10.0-957.1.3.el7.x86_64  | 3.10.0-693.21.1.el7.x86_64 |
+   | kernel-devel | 3.10.0-957.5.1.el7.x86_64 | 3.10.0-862.11.6.el7.x86_64, 3.10.0-957.1.3.el7.x86_64 | 3.10.0-693.21.1.el7.x86_64 |
+   | LIBSTDC++ | libstdc++-4.8.5-36.el7.x86_64 | libstdc++-4.8.5-36.el7.x86_64 | libstdc++-4.8.5-16.el7_4.2.x86_64 |
+
 ## Release 1.4.8 (See [ERRATA](./ERRATA.md) for unsupported features)
-  * FPGA developer kit supports Xilinx SDx/Vivado 2018.3
+ * FPGA developer kit supports Xilinx SDx/Vivado 2018.3
     * We recommend developers upgrade to v1.4.8 to benefit from the new features, bug fixes, and optimizations. To upgrade, use [Developer AMI v1.6.0](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) on AWS Marketplace.  The Developer Kit scripts (hdk_setup.sh or sdaccel_setup.sh) will detect the tool version and update the environment based on requirements needed for Xilinx 2018.3 tools. 
  * Ease of Use features:
     * Support for importing results into SDx GUI - By importing results from a script-based flow into SDx IDE, developers can leverage the tools for debug/profiling while keeping flexibility of the script-based flow
@@ -58,9 +80,6 @@
    | LIBSTDC++ | libstdc++-4.8.5-36.el7.x86_64 | libstdc++-4.8.5-36.el7.x86_64 | libstdc++-4.8.5-16.el7_4.2.x86_64 |
 
 
-
-
-
 ## Release 1.4.7 (See [ERRATA](./ERRATA.md) for unsupported features)
 
   * Adds [Xilinx Runtime (XRT)](https://github.com/Xilinx/XRT/releases/tag/2018.2_XDF.RC5) Support for Linux kernel 3.10.0-957.1.3.el7.x86_64 & Centos 7.6

diff --git a/hdk/cl/CHECKLIST_BEFORE_BUILDING_CL.md b/hdk/cl/CHECKLIST_BEFORE_BUILDING_CL.md
@@ -11,3 +11,5 @@ This checklist includes important items that the developer should check before c
 5. Update the timing and placement constraints under `$CL_DIR/build/constraints` for your design specific changes.
 
 6. Update `$CL_DIR/build/scripts/create_dcp_from_cl.tcl` for your design specific changes, specifically around IP sources and xdc files, and your specific design xdc files.
+
+7. If you ran the HLx flow before, make sure you [follow the steps to switch between HLx and HDK flows](../docs/IPI_GUI_Vivado_Setup.md#hlxhdk_switch)
diff --git a/hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma_hwsw_cosim.c b/hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma_hwsw_cosim.c
@@ -167,6 +167,7 @@ int dma_example_hwsw_cosim(int slot_id, size_t buffer_size)
     setup_send_rdbuf_to_c(read_buffer, buffer_size);
     printf("Starting DDR init...\n");
     init_ddr();
+    deselect_atg_hw();
     printf("Done DDR init...\n");
 #endif
     printf("filling buffer with  random data...\n") ;

diff --git a/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.questa b/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.questa
@@ -26,7 +26,7 @@ compile: $(COMPLIB_DIR)
 	mkdir -p $(SIM_DIR)
 	cd ${SIM_DIR} && ln -s -f ../questa_complib/modelsim.ini 
 	cd $(SIM_DIR) && vlog $(C_FILES) -ccflags "-I$(C_SDK_USR_INC_DIR)" -ccflags "-I$(C_SDK_USR_UTILS_DIR)" -ccflags "-I$(C_COMMON_DIR)/include" -ccflags "-I$(C_COMMON_DIR)/src" -ccflags "-DSV_TEST" -ccflags "-DSCOPE" -ccflags "-DQUESTA_SIM" -ccflags "-DINT_MAIN" -ccflags "-I$(C_INC_DIR)"
-	cd $(SIM_DIR) && vlog -suppress 2732 +define+DMA_TEST $(DEFAULT_DEFINES) -mfcu -sv -64 -timescale 1ps/1ps -93 -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/secureip -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f
+	cd $(SIM_DIR) && vlog +define+DMA_TEST $(DEFAULT_DEFINES) -mfcu -sv -64 -timescale 1ps/1ps -93 -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/secureip -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f
 
 run:
 ifeq ($(VIVADO_TOOL_VERSION), v2017.4)

diff --git a/hdk/cl/examples/cl_dram_dma/verif/tests/test_dma_pcim_concurrent.sv b/hdk/cl/examples/cl_dram_dma/verif/tests/test_dma_pcim_concurrent.sv
@@ -213,21 +213,39 @@ module test_dma_pcim_concurrent();
 
          // Number of instructions, zero based ([31:16] for read, [15:0] for write)
          tb.poke_ocl(.addr(`NUM_INST), .data(32'h0000_0000));
-
+        
          // Start writes and reads
-         tb.poke_ocl(.addr(`CNTL_REG), .data(`WR_START_BIT | `RD_START_BIT));
-
-         $display("[%t] : Waiting for PCIe write and read activity to complete", $realtime);
+         tb.poke_ocl(.addr(`CNTL_REG), .data(`WR_START_BIT));
+	 //Even in SYNC mode ATG doesn't wait for write response before issuing read transactions.
+	 // adding 500ns wait to account for random back pressure from sh_bfm on write address & write data channels.
+         $display("[%t] : Waiting for PCIe write activity to complete", $realtime);
          #500ns;
+         timeout_count = 0;
 
+         do begin
+            tb.peek_ocl(.addr(`CNTL_REG), .data(read_data));
+            timeout_count++;
+         end while ((read_data[2:0] !== 3'b000) && (timeout_count < 100));
+
+         if ((timeout_count == 100) && (read_data[2:0] !== 3'b000)) begin
+            $error("[%t] : *** ERROR *** Timeout waiting for writes to complete.", $realtime);
+            error_count++;
+         end 
+
+         tb.poke_ocl(.addr(`CNTL_REG), .data(`RD_START_BIT));
+	 // adding 500ns wait to account for random back pressure from sh_bfm on read request channel.
+
+         $display("[%t] : Waiting for PCIe read activity to complete", $realtime);
+         #500ns;
+
          timeout_count = 0;
          do begin
             tb.peek_ocl(.addr(`CNTL_REG), .data(read_data));
             timeout_count++;
          end while ((read_data[2:0] !== 3'b000) && (timeout_count < 100));
 
          if ((timeout_count == 100) && (read_data[2:0] !== 3'b000)) begin
-            $display("[%t] : *** ERROR *** Timeout waiting for writes and reads to complete.", $realtime);
+            $error("[%t] : *** ERROR *** Timeout waiting for reads to complete.", $realtime);
             error_count++;
          end else begin
             // Stop reads and writes ([1] for reads, [0] for writes)
@@ -242,7 +260,7 @@ module test_dma_pcim_concurrent();
             tb.peek_ocl(.addr(`WR_CYCLE_CNT_HIGH), .data(read_data));
             cycle_count[63:32] = read_data;
             if (cycle_count == 64'h0) begin
-               $display("[%t] : *** ERROR *** Write Timer value was 0x0 at end of test.", $realtime);
+               $error("[%t] : *** ERROR *** Write Timer value was 0x0 at end of test.", $realtime);
                error_count++;
             end
 
@@ -253,7 +271,7 @@ module test_dma_pcim_concurrent();
             tb.peek_ocl(.addr(`RD_CYCLE_CNT_HIGH), .data(read_data));
             cycle_count[63:32] = read_data;
             if (cycle_count == 64'h0) begin
-               $display("[%t] : *** ERROR *** Read Timer value was 0x0 at end of test.", $realtime);
+               $error("[%t] : *** ERROR *** Read Timer value was 0x0 at end of test.", $realtime);
                error_count++;
             end
 
@@ -268,7 +286,7 @@ module test_dma_pcim_concurrent();
                error_addr[63:32] = read_data;
                tb.peek_ocl(.addr(`RD_ERR_INDEX), .data(read_data));
                error_index = read_data[3:0];
-               $display("[%t] : *** ERROR *** Read compare error from address 0x%016x, index 0x%1x", $realtime, error_addr, error_index);
+               $error("[%t] : *** ERROR *** Read compare error from address 0x%016x, index 0x%1x", $realtime, error_addr, error_index);
                error_count++;
             end
          end // else: !if((timeout_count == 100) && (read_data[2:0] !== 3'b000))
@@ -288,7 +306,7 @@ module test_dma_pcim_concurrent();
       $display("[%t] : Detected %3d errors during this test", $realtime, error_count);
 
       if (fail || (tb.chk_prot_err_stat())) begin
-         $display("[%t] : *** TEST FAILED ***", $realtime);
+         $error("[%t] : *** TEST FAILED ***", $realtime);
       end else begin
          $display("[%t] : *** TEST PASSED ***", $realtime);
       end
Original file line number	Diff line number	Diff line change
Expand Up		@@ -11,3 +11,5 @@ This checklist includes important items that the developer should check before c
		5. Update the timing and placement constraints under `$CL_DIR/build/constraints` for your design specific changes.

		6. Update `$CL_DIR/build/scripts/create_dcp_from_cl.tcl` for your design specific changes, specifically around IP sources and xdc files, and your specific design xdc files.

		7. If you ran the HLx flow before, make sure you [follow the steps to switch between HLx and HDK flows](../docs/IPI_GUI_Vivado_Setup.md#hlxhdk_switch)