Record: Allow to configure Perf Events based on Model

aws · Dec 6, 2023 · 5a3ab90 · 5a3ab90
1 parent ce4ee5e
commit 5a3ab90
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Showing 8 changed files with 269 additions and 26 deletions.
diff --git a/Cargo.lock b/Cargo.lock
diff --git a/Cargo.toml b/Cargo.toml
@@ -43,10 +43,10 @@ strum_macros = "0.24"
 sysctl = "*"
 perf-event2 = "0.7.1"
 num_cpus = "1.0"
-raw-cpuid = "10.6.0"
 libc = "0.2"
 flate2 = "1.0.26"
 tar = "0.4.38"
 infer = "0.13.0"
 bincode = "1.3.3"
 inferno = "0.11.15"
+indexmap = "2.1.0"
diff --git a/src/data.rs b/src/data.rs
@@ -4,8 +4,10 @@ pub mod diskstats;
 pub mod flamegraphs;
 #[cfg(target_arch = "aarch64")]
 pub mod grv_perf_events;
+pub mod intel_icelake_perf_events;
 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 pub mod intel_perf_events;
+pub mod intel_sapphire_rapids_perf_events;
 pub mod interrupts;
 pub mod kernel_config;
 pub mod meminfodata;
@@ -15,6 +17,7 @@ pub mod perf_stat;
 pub mod processes;
 pub mod sysctldata;
 pub mod systeminfo;
+pub mod utils;
 pub mod vmstat;
 
 use crate::visualizer::{GetData, ReportParams};

diff --git a/src/data/intel_icelake_perf_events.rs b/src/data/intel_icelake_perf_events.rs
@@ -0,0 +1,40 @@
+use crate::data::perf_stat::{NamedCtr, NamedTypeCtr, PerfType};
+
+static CYCLES: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Cycles",
+    config: 0x3c,
+};
+static SLOTS: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Slots",
+    config: 0x01a4,
+};
+static STALL_FRONTEND: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Frontend-Stalls",
+    config: 0x500019c,
+};
+static STALL_BACKEND: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Backend-Stalls",
+    config: 0x02a4,
+};
+
+lazy_static! {
+    pub static ref ICX_CTRS: Vec<NamedCtr<'static>> = [
+        NamedCtr {
+            name: "stall-frontend-pkc",
+            nrs: vec![STALL_FRONTEND],
+            drs: vec![CYCLES],
+            scale: 1000
+        },
+        NamedCtr {
+            name: "stall-backend-pkc",
+            nrs: vec![STALL_BACKEND],
+            drs: vec![SLOTS],
+            scale: 1000
+        },
+    ]
+    .to_vec();
+}
diff --git a/src/data/intel_perf_events.rs b/src/data/intel_perf_events.rs
@@ -39,7 +39,7 @@ static L1_INSTRUCTIONS: NamedTypeCtr = NamedTypeCtr {
 static BACKEND_STALLS: NamedTypeCtr = NamedTypeCtr {
     perf_type: PerfType::RAW,
     name: "Backend-Stalls",
-    config: 0x10a2,
+    config: 0x01a2,
 };
 static L3: NamedTypeCtr = NamedTypeCtr {
     perf_type: PerfType::RAW,

diff --git a/src/data/intel_sapphire_rapids_perf_events.rs b/src/data/intel_sapphire_rapids_perf_events.rs
@@ -0,0 +1,122 @@
+use crate::data::perf_stat::{NamedCtr, NamedTypeCtr, PerfType};
+
+static INSTRUCTIONS: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Instructions",
+    config: 0xc0,
+};
+static CYCLES: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Cycles",
+    config: 0x3c,
+};
+static SLOTS: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Slots",
+    config: 0x01a4,
+};
+static L2: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "L2",
+    config: 0x1f25,
+};
+static INSTRUCTION_TLB: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Instruction-TLB",
+    config: 0x2011,
+};
+static INSTRUCTION_TLB_TW: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Instruction-TLB-TW",
+    config: 0x0e11,
+};
+static DATA_RD_TLB: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Data-RD-TLB",
+    config: 0x2012,
+};
+static DATA_ST_TLB: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Data-ST-TLB",
+    config: 0x2013,
+};
+static DATA_RD_TLB_TW: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Data-RD-TLB-TW",
+    config: 0x0e12,
+};
+static DATA_ST_TLB_TW: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Data-ST-TLB-TW",
+    config: 0x0e13,
+};
+static STALL_FRONTEND: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Frontend-Stalls",
+    config: 0x600019c,
+};
+static STALL_BACKEND: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Backend-Stalls",
+    config: 0x02a4,
+};
+
+lazy_static! {
+    pub static ref SPR_CTRS: Vec<NamedCtr<'static>> = [
+        NamedCtr {
+            name: "l2-mpki",
+            nrs: vec![L2],
+            drs: vec![INSTRUCTIONS],
+            scale: 1000
+        },
+        NamedCtr {
+            name: "inst-tlb-mpki",
+            nrs: vec![INSTRUCTION_TLB],
+            drs: vec![INSTRUCTIONS],
+            scale: 1000
+        },
+        NamedCtr {
+            name: "inst-tlb-tw-pki",
+            nrs: vec![INSTRUCTION_TLB_TW],
+            drs: vec![INSTRUCTIONS],
+            scale: 1000
+        },
+        NamedCtr {
+            name: "data-rd-tlb-mpki",
+            nrs: vec![DATA_RD_TLB],
+            drs: vec![INSTRUCTIONS],
+            scale: 1000
+        },
+        NamedCtr {
+            name: "data-st-tlb-mpki",
+            nrs: vec![DATA_ST_TLB],
+            drs: vec![INSTRUCTIONS],
+            scale: 1000
+        },
+        NamedCtr {
+            name: "data-rd-tlb-tw-pki",
+            nrs: vec![DATA_RD_TLB_TW],
+            drs: vec![INSTRUCTIONS],
+            scale: 1000
+        },
+        NamedCtr {
+            name: "data-st-tlb-tw-pki",
+            nrs: vec![DATA_ST_TLB_TW],
+            drs: vec![INSTRUCTIONS],
+            scale: 1000
+        },
+        NamedCtr {
+            name: "stall-frontend-pkc",
+            nrs: vec![STALL_FRONTEND],
+            drs: vec![CYCLES],
+            scale: 1000
+        },
+        NamedCtr {
+            name: "stall-backend-pkc",
+            nrs: vec![STALL_BACKEND],
+            drs: vec![SLOTS],
+            scale: 1000
+        },
+    ]
+    .to_vec();
+}