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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,35 @@ | ||
| /** | ||
| * @file include/retdec/capstone2llvmir/arm64/arm64.h | ||
| * @brief ARM64 specialization of translator's abstract public interface. | ||
| * @copyright (c) 2018 Avast Software, licensed under the MIT license | ||
| */ | ||
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| #ifndef RETDEC_CAPSTONE2LLVMIR_ARM64_ARM64_H | ||
| #define RETDEC_CAPSTONE2LLVMIR_ARM64_ARM64_H | ||
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| #include "retdec/capstone2llvmir/arm64/arm64_defs.h" | ||
| #include "retdec/capstone2llvmir/capstone2llvmir.h" | ||
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| namespace retdec { | ||
| namespace capstone2llvmir { | ||
|
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| /** | ||
| * ARM64 specialization of translator's abstract public interface. | ||
| */ | ||
| class Capstone2LlvmIrTranslatorArm64 : virtual public Capstone2LlvmIrTranslator | ||
| { | ||
| public: | ||
| virtual ~Capstone2LlvmIrTranslatorArm64() {}; | ||
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| public: | ||
| /** | ||
| * @return Capstone register that is parent to the specified Capstone | ||
| * register @p r. Register can be its own parent. | ||
| */ | ||
| virtual uint32_t getParentRegister(uint32_t r) const = 0; | ||
| }; | ||
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| } // namespace capstone2llvmir | ||
| } // namespace retdec | ||
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| #endif /* RETDEC_CAPSTONE2LLVMIR_ARM64_ARM64_H */ |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,21 @@ | ||
| /** | ||
| * @file include/retdec/capstone2llvmir/arm64/arm64_defs.h | ||
| * @brief Additional (on top of Capstone) definitions for ARM64 translator. | ||
| * @copyright (c) 2018 Avast Software, licensed under the MIT license | ||
| */ | ||
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| #ifndef RETDEC_CAPSTONE2LLVMIR_ARM64_ARM64_DEFS_H | ||
| #define RETDEC_CAPSTONE2LLVMIR_ARM64_ARM64_DEFS_H | ||
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| #include <capstone/arm64.h> | ||
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| enum arm64_reg_cpsr_flags | ||
| { | ||
| ARM64_REG_CPSR_N = ARM64_REG_ENDING + 1, | ||
| ARM64_REG_CPSR_Z, | ||
| ARM64_REG_CPSR_C, | ||
| ARM64_REG_CPSR_V, | ||
| ARM64_REG_PC, | ||
| }; | ||
|
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| #endif /* RETDEC_CAPSTONE2LLVMIR_ARM64_ARM64_DEFS_H */ |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,111 @@ | ||
| /** | ||
| * @file src/bin2llvmir/optimizations/decoder/arm64.cpp | ||
| * @brief Decoding methods specific to ARM64 architecture. | ||
| * @copyright (c) 2018 Avast Software, licensed under the MIT license | ||
| */ | ||
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| #include "retdec/bin2llvmir/optimizations/decoder/decoder.h" | ||
| #include "retdec/bin2llvmir/utils/capstone.h" | ||
| #include "retdec/utils/string.h" | ||
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| using namespace retdec::utils; | ||
| using namespace retdec::capstone2llvmir; | ||
| using namespace llvm; | ||
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| namespace retdec { | ||
| namespace bin2llvmir { | ||
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| bool insnWrittesPcArm64(csh& ce, cs_insn* insn) | ||
| { | ||
| // Aarch64 reference manual states: | ||
| // Software cannot write directly to the PC. It can only | ||
| // be updated on a branch, exception entry or exception return. | ||
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| // Set of instructions that can modify PC | ||
| const std::set<unsigned int> branch_instructions = { | ||
| ARM64_INS_B, | ||
| ARM64_INS_CBNZ, | ||
| ARM64_INS_CBZ, | ||
| ARM64_INS_TBNZ, | ||
| ARM64_INS_TBZ, | ||
| ARM64_INS_BL, | ||
| ARM64_INS_BLR, | ||
| ARM64_INS_BR, | ||
| ARM64_INS_RET, | ||
| ARM64_INS_ERET, | ||
| }; | ||
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| return (branch_instructions.count(insn->id) != 0); | ||
| } | ||
|
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| bool looksLikeArm64FunctionStart(cs_insn* insn) | ||
| { | ||
| // Create stack frame 'stp x29, x30, [sp, -48]!' | ||
| return insn->id == ARM64_INS_STP; | ||
| } | ||
|
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| std::size_t Decoder::decodeJumpTargetDryRun_arm64( | ||
| const JumpTarget& jt, | ||
| ByteData bytes, | ||
| bool strict) | ||
| { | ||
|
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| if (strict) | ||
| { | ||
| return true; | ||
| } | ||
|
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| static csh ce = _c2l->getCapstoneEngine(); | ||
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| uint64_t addr = jt.getAddress(); | ||
| std::size_t nops = 0; | ||
| bool first = true; | ||
| // bytes.first -> Code | ||
| // bytes.second -> Code size | ||
| // addr -> Address of first instruction | ||
| while (cs_disasm_iter(ce, &bytes.first, &bytes.second, &addr, _dryCsInsn)) | ||
| { | ||
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| if (strict && first && !looksLikeArm64FunctionStart(_dryCsInsn)) | ||
| { | ||
| return true; | ||
| } | ||
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| if (jt.getType() == JumpTarget::eType::LEFTOVER | ||
| && (first || nops > 0) | ||
| && _abi->isNopInstruction(_dryCsInsn)) | ||
| { | ||
| nops += _dryCsInsn->size; | ||
| } | ||
| else if (jt.getType() == JumpTarget::eType::LEFTOVER | ||
| && nops > 0) | ||
| { | ||
| return nops; | ||
| } | ||
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| if (_c2l->isControlFlowInstruction(*_dryCsInsn) | ||
| || insnWrittesPcArm64(ce, _dryCsInsn)) | ||
| { | ||
| return false; | ||
| } | ||
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| first = false; | ||
| } | ||
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| if (nops > 0) | ||
| { | ||
| return nops; | ||
| } | ||
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| // There is a BB right after, that is not a function start. | ||
| // | ||
| if (getBasicBlockAtAddress(addr) && getFunctionAtAddress(addr) == nullptr) | ||
| { | ||
| return false; | ||
| } | ||
|
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| return true; | ||
| } | ||
|
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| } // namespace bin2llvmir | ||
| } // namespace retdec |
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