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Recompile variants
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@facchinm
facchinm committed Sep 12, 2022
1 parent 32e855a commit b18ad7a
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Showing 27 changed files with 47 additions and 71 deletions.
43 changes: 0 additions & 43 deletions ...uino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_lfn.h
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4 changes: 2 additions & 2 deletions variants/ARDUINO_NANO33BLE/defines.txt
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Expand Up @@ -34,7 +34,7 @@
-DFEATURE_STORAGE=1
-D__FPU_PRESENT=1
-D__MBED__=1
-DMBED_BUILD_TIMESTAMP=1657634139.8909109
-DMBED_BUILD_TIMESTAMP=1662124743.5782256
-D__MBED_CMSIS_RTOS_CM
-DMBED_MPU_CUSTOM
-DMBED_TICKLESS
Expand Down Expand Up @@ -66,6 +66,6 @@
-DWSF_MAX_HANDLERS=10
-DMBED_NO_GLOBAL_USING_DIRECTIVE=1
-DCORE_MAJOR=3
-DCORE_MINOR=2
-DCORE_MINOR=3
-DCORE_PATCH=0
-DUSE_ARDUINO_PINOUT
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4 changes: 2 additions & 2 deletions variants/EDGE_CONTROL/defines.txt
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Expand Up @@ -38,7 +38,7 @@
-DFEATURE_STORAGE=1
-D__FPU_PRESENT=1
-D__MBED__=1
-DMBED_BUILD_TIMESTAMP=1657634299.426995
-DMBED_BUILD_TIMESTAMP=1662124896.2555702
-D__MBED_CMSIS_RTOS_CM
-DMBED_MPU_CUSTOM
-DMBED_TICKLESS
Expand Down Expand Up @@ -70,6 +70,6 @@
-DWSF_MAX_HANDLERS=10
-DMBED_NO_GLOBAL_USING_DIRECTIVE=1
-DCORE_MAJOR=3
-DCORE_MINOR=2
-DCORE_MINOR=3
-DCORE_PATCH=0
-DUSE_ARDUINO_PINOUT
Binary file modified variants/EDGE_CONTROL/libs/libmbed.a
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4 changes: 2 additions & 2 deletions variants/NANO_RP2040_CONNECT/defines.txt
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Expand Up @@ -20,7 +20,7 @@
-DDEVICE_USTICKER=1
-DDEVICE_WATCHDOG=1
-D__MBED__=1
-DMBED_BUILD_TIMESTAMP=1657634119.7651937
-DMBED_BUILD_TIMESTAMP=1662124722.8055787
-D__MBED_CMSIS_RTOS_CM
-DMBED_MPU_CUSTOM
-DMBEDTLS_ENTROPY_NV_SEED
Expand All @@ -45,6 +45,6 @@
-DTOOLCHAIN_GCC_ARM
-DMBED_NO_GLOBAL_USING_DIRECTIVE=1
-DCORE_MAJOR=3
-DCORE_MINOR=2
-DCORE_MINOR=3
-DCORE_PATCH=0
-DUSE_ARDUINO_PINOUT
Binary file modified variants/NANO_RP2040_CONNECT/libs/libmbed.a
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4 changes: 2 additions & 2 deletions variants/NICLA/defines.txt
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Expand Up @@ -33,7 +33,7 @@
-DFEATURE_BLE=1
-D__FPU_PRESENT=1
-D__MBED__=1
-DMBED_BUILD_TIMESTAMP=1657634333.4979331
-DMBED_BUILD_TIMESTAMP=1662124928.8471718
-D__MBED_CMSIS_RTOS_CM
-DMBED_MPU_CUSTOM
-DMBED_TICKLESS
Expand Down Expand Up @@ -76,6 +76,6 @@
-DTOOLCHAIN_GCC_ARM
-DMBED_NO_GLOBAL_USING_DIRECTIVE=1
-DCORE_MAJOR=3
-DCORE_MINOR=2
-DCORE_MINOR=3
-DCORE_PATCH=0
-DUSE_ARDUINO_PINOUT
Binary file modified variants/NICLA/libs/libmbed.a
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4 changes: 2 additions & 2 deletions variants/NICLA_VISION/defines.txt
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Expand Up @@ -45,7 +45,7 @@
-DFLOW_SILENT
-D__FPU_PRESENT=1
-D__MBED__=1
-DMBED_BUILD_TIMESTAMP=1657634365.6035068
-DMBED_BUILD_TIMESTAMP=1662124959.407307
-D__MBED_CMSIS_RTOS_CM
-DMBED_TICKLESS
-DMBEDTLS_FS_IO
Expand Down Expand Up @@ -84,6 +84,6 @@
-DVIRTIO_MASTER_ONLY
-DMBED_NO_GLOBAL_USING_DIRECTIVE=1
-DCORE_MAJOR=3
-DCORE_MINOR=2
-DCORE_MINOR=3
-DCORE_PATCH=0
-DUSE_ARDUINO_PINOUT
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4 changes: 2 additions & 2 deletions variants/PORTENTA_H7_M4/defines.txt
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Expand Up @@ -44,7 +44,7 @@
-DFEATURE_BLE=1
-D__FPU_PRESENT=1
-D__MBED__=1
-DMBED_BUILD_TIMESTAMP=1657634246.2822626
-DMBED_BUILD_TIMESTAMP=1662124845.668187
-D__MBED_CMSIS_RTOS_CM
-DMBED_MPU_CUSTOM
-DMBED_TICKLESS
Expand Down Expand Up @@ -83,6 +83,6 @@
-DVIRTIO_SLAVE_ONLY
-DMBED_NO_GLOBAL_USING_DIRECTIVE=1
-DCORE_MAJOR=3
-DCORE_MINOR=2
-DCORE_MINOR=3
-DCORE_PATCH=0
-DUSE_ARDUINO_PINOUT
Binary file modified variants/PORTENTA_H7_M4/libs/libmbed.a
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8 changes: 7 additions & 1 deletion variants/PORTENTA_H7_M4/linker_script.ld
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@@ -1,6 +1,6 @@
MEMORY
{
FLASH (rx) : ORIGIN = CM4_BINARY_START, LENGTH = CM4_BINARY_END - CM4_BINARY_START
FLASH (rx) : ORIGIN = CM4_BINARY_START, LENGTH = 0x100000
RAM (rwx) : ORIGIN = 0x10000000 + (((166 * 4) + 7) & 0xFFFFFFF8), LENGTH = 0x48000 - (((166 * 4) + 7) & 0xFFFFFFF8)
RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
}
Expand Down Expand Up @@ -93,6 +93,12 @@ SECTIONS
. = ABSOLUTE(0x3800FC00);
*(.pdm_buffer)
} > RAM_D3
_dtcm_lma = __etext + SIZEOF(.data);
.dtcm : AT(_dtcm_lma) {
_sdtcm = .;
*(.dtcm*)
_edtcm = .;
} > DTCMRAM
.heap (COPY):
{
__end__ = .;
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2 changes: 1 addition & 1 deletion variants/PORTENTA_H7_M4/mbed_config.h
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Expand Up @@ -380,7 +380,7 @@
#define MBED_CONF_TARGET_LPTICKER_LPTIM 1 // set by target:MCU_STM32H7
#define MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK 1 // set by target:MCU_STM32
#define MBED_CONF_TARGET_LPUART_CLOCK_SOURCE USE_LPUART_CLK_LSE|USE_LPUART_CLK_PCLK1|USE_LPUART_CLK_PCLK3 // set by target:MCU_STM32
#define MBED_CONF_TARGET_LSE_AVAILABLE 0 // set by target:PORTENTA_H7
#define MBED_CONF_TARGET_LSE_AVAILABLE 1 // set by target:PORTENTA_H7
#define MBED_CONF_TARGET_LSE_BYPASS 1 // set by target:PORTENTA_H7
#define MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL RCC_LSEDRIVE_LOW // set by target:MCU_STM32H7
#define MBED_CONF_TARGET_MPU_ROM_END 0x0fffffff // set by target:Target
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4 changes: 2 additions & 2 deletions variants/PORTENTA_H7_M7/cflags.txt
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Expand Up @@ -3,12 +3,12 @@
-DAPPLICATION_ADDR=0x8040000
-DAPPLICATION_RAM_ADDR=0x24000000
-DAPPLICATION_RAM_SIZE=0x80000
-DAPPLICATION_SIZE=0xc0000
-DAPPLICATION_SIZE=0x1c0000
-DMBED_RAM1_SIZE=0x80000
-DMBED_RAM1_START=0x24000000
-DMBED_RAM_SIZE=0x80000
-DMBED_RAM_START=0x24000000
-DMBED_ROM_SIZE=0x100000
-DMBED_ROM_SIZE=0x200000
-DMBED_ROM_START=0x8000000
-DMBED_TRAP_ERRORS_ENABLED=1
-Os
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4 changes: 2 additions & 2 deletions variants/PORTENTA_H7_M7/cxxflags.txt
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Expand Up @@ -5,12 +5,12 @@
-DAPPLICATION_ADDR=0x8040000
-DAPPLICATION_RAM_ADDR=0x24000000
-DAPPLICATION_RAM_SIZE=0x80000
-DAPPLICATION_SIZE=0xc0000
-DAPPLICATION_SIZE=0x1c0000
-DMBED_RAM1_SIZE=0x80000
-DMBED_RAM1_START=0x24000000
-DMBED_RAM_SIZE=0x80000
-DMBED_RAM_START=0x24000000
-DMBED_ROM_SIZE=0x100000
-DMBED_ROM_SIZE=0x200000
-DMBED_ROM_START=0x8000000
-DMBED_TRAP_ERRORS_ENABLED=1
-Os
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5 changes: 3 additions & 2 deletions variants/PORTENTA_H7_M7/defines.txt
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Expand Up @@ -44,8 +44,9 @@
-DEXTRA_IDLE_STACK_REQUIRED
-DFEATURE_BLE=1
-D__FPU_PRESENT=1
-DLSE_STARTUP_TIMEOUT=200
-D__MBED__=1
-DMBED_BUILD_TIMESTAMP=1657634193.764244
-DMBED_BUILD_TIMESTAMP=1662124795.1873505
-D__MBED_CMSIS_RTOS_CM
-DMBED_TICKLESS
-DMBEDTLS_FS_IO
Expand Down Expand Up @@ -83,6 +84,6 @@
-DVIRTIO_MASTER_ONLY
-DMBED_NO_GLOBAL_USING_DIRECTIVE=1
-DCORE_MAJOR=3
-DCORE_MINOR=2
-DCORE_MINOR=3
-DCORE_PATCH=0
-DUSE_ARDUINO_PINOUT
4 changes: 2 additions & 2 deletions variants/PORTENTA_H7_M7/ldflags.txt
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@@ -1,11 +1,11 @@
-DMBED_APP_SIZE=0xc0000
-DMBED_APP_SIZE=0x1c0000
-DMBED_APP_START=0x8040000
-DMBED_BOOT_STACK_SIZE=1024
-DMBED_RAM1_SIZE=0x80000
-DMBED_RAM1_START=0x24000000
-DMBED_RAM_SIZE=0x80000
-DMBED_RAM_START=0x24000000
-DMBED_ROM_SIZE=0x100000
-DMBED_ROM_SIZE=0x200000
-DMBED_ROM_START=0x8000000
-DXIP_ENABLE=0
-Wl,--gc-sections
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Binary file modified variants/PORTENTA_H7_M7/libs/libmbed.a
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6 changes: 6 additions & 0 deletions variants/PORTENTA_H7_M7/linker_script.ld
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Expand Up @@ -96,6 +96,12 @@ SECTIONS
. = ABSOLUTE(0x3800FC00);
*(.pdm_buffer)
} > RAM_D3
_dtcm_lma = __etext + SIZEOF(.data);
.dtcm : AT(_dtcm_lma) {
_sdtcm = .;
*(.dtcm*)
_edtcm = .;
} > DTCMRAM
.heap (COPY):
{
__end__ = .;
Expand Down
2 changes: 1 addition & 1 deletion variants/PORTENTA_H7_M7/mbed_config.h
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Expand Up @@ -382,7 +382,7 @@
#define MBED_CONF_TARGET_LPTICKER_LPTIM 1 // set by target:MCU_STM32H7
#define MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK 1 // set by target:MCU_STM32
#define MBED_CONF_TARGET_LPUART_CLOCK_SOURCE USE_LPUART_CLK_LSE|USE_LPUART_CLK_PCLK1|USE_LPUART_CLK_PCLK3 // set by target:MCU_STM32
#define MBED_CONF_TARGET_LSE_AVAILABLE 0 // set by target:PORTENTA_H7
#define MBED_CONF_TARGET_LSE_AVAILABLE 1 // set by target:PORTENTA_H7
#define MBED_CONF_TARGET_LSE_BYPASS 1 // set by target:PORTENTA_H7
#define MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL RCC_LSEDRIVE_LOW // set by target:MCU_STM32H7
#define MBED_CONF_TARGET_MPU_ROM_END 0x0fffffff // set by target:Target
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4 changes: 2 additions & 2 deletions variants/PORTENTA_X8/defines.txt
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Expand Up @@ -34,7 +34,7 @@
-DEXTRA_IDLE_STACK_REQUIRED
-D__FPU_PRESENT=1
-D__MBED__=1
-DMBED_BUILD_TIMESTAMP=1657634421.4872477
-DMBED_BUILD_TIMESTAMP=1662125012.238662
-D__MBED_CMSIS_RTOS_CM
-DMBED_MPU_CUSTOM
-DMBED_TICKLESS
Expand Down Expand Up @@ -71,6 +71,6 @@
-DVIRTIO_SLAVE_ONLY
-DMBED_NO_GLOBAL_USING_DIRECTIVE=1
-DCORE_MAJOR=3
-DCORE_MINOR=2
-DCORE_MINOR=3
-DCORE_PATCH=0
-DUSE_ARDUINO_PINOUT
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8 changes: 7 additions & 1 deletion variants/PORTENTA_X8/linker_script.ld
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@@ -1,6 +1,6 @@
MEMORY
{
FLASH (rx) : ORIGIN = CM4_BINARY_START, LENGTH = CM4_BINARY_END - CM4_BINARY_START
FLASH (rx) : ORIGIN = CM4_BINARY_START, LENGTH = 0x100000
RAM (rwx) : ORIGIN = 0x10000000 + (((166 * 4) + 7) & 0xFFFFFFF8), LENGTH = 0x48000 - (((166 * 4) + 7) & 0xFFFFFFF8)
RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
}
Expand Down Expand Up @@ -93,6 +93,12 @@ SECTIONS
. = ABSOLUTE(0x3800FC00);
*(.pdm_buffer)
} > RAM_D3
_dtcm_lma = __etext + SIZEOF(.data);
.dtcm : AT(_dtcm_lma) {
_sdtcm = .;
*(.dtcm*)
_edtcm = .;
} > DTCMRAM
.heap (COPY):
{
__end__ = .;
Expand Down
4 changes: 2 additions & 2 deletions variants/RASPBERRY_PI_PICO/defines.txt
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Expand Up @@ -20,7 +20,7 @@
-DDEVICE_USTICKER=1
-DDEVICE_WATCHDOG=1
-D__MBED__=1
-DMBED_BUILD_TIMESTAMP=1657634171.1910558
-DMBED_BUILD_TIMESTAMP=1662124773.2915711
-D__MBED_CMSIS_RTOS_CM
-DMBED_MPU_CUSTOM
-DMBEDTLS_ENTROPY_NV_SEED
Expand All @@ -44,6 +44,6 @@
-DTOOLCHAIN_GCC_ARM
-DMBED_NO_GLOBAL_USING_DIRECTIVE=1
-DCORE_MAJOR=3
-DCORE_MINOR=2
-DCORE_MINOR=3
-DCORE_PATCH=0
-DUSE_ARDUINO_PINOUT
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