[VTA][TSIM] update app example

vta/apps/tsim_example/CMakeLists.txt

@@ -34,6 +34,10 @@ if (CMAKE_CXX_COMPILER_ID MATCHES "GNU" AND
   set(CMAKE_CXX_FLAGS "-faligned-new ${CMAKE_CXX_FLAGS}")
 endif()
 
-# Module rules
-include(cmake/modules/hw.cmake)
-include(cmake/modules/sw.cmake)
+file(GLOB TSIM_SW_SRC src/driver.cc)
+add_library(sw SHARED ${TSIM_SW_SRC})
+target_include_directories(sw PRIVATE ${VTA_DIR}/include)
+
+if(APPLE)
+  set_target_properties(sw PROPERTIES LINK_FLAGS "-undefined dynamic_lookup")
+endif(APPLE)

vta/apps/tsim_example/Makefile

@@ -17,20 +17,32 @@
 
 export PYTHONPATH:=$(PWD)/python:$(PYTHONPATH)
 
-BUILD_DIR = $(shell python3 config/config.py --get-build-name)
+BUILD_NAME = build
+build_dir = $(abspath .)/$(BUILD_NAME)
 
-default: cmake run
+default: verilog driver run_verilog
 
+run_chisel: chisel driver 
+	python3 tests/python/chisel_accel.py
+
 .PHONY: cmake
 
-cmake: | $(BUILD_DIR)
-	cd $(BUILD_DIR) && cmake .. && make
+driver: | $(build_dir)
+	cd $(build_dir) && cmake .. && make
 
-$(BUILD_DIR):
+$(build_dir):
 	mkdir -p $@
 
-run:
-	python3 tests/python/add_by_one.py | grep PASS
+verilog:
+	make -C hardware/verilog
+
+chisel:
+	make -C hardware/chisel
+
+run_verilog:
+	python3 tests/python/verilog_accel.py
 
 clean:
-	-rm -rf $(BUILD_DIR)
+	-rm -rf $(build_dir)
+	make -C hardware/chisel clean
+	make -C hardware/verilog clean

vta/apps/tsim_example/README.md

@@ -49,29 +49,25 @@ sudo apt install verilator sbt
 ## Setup in TVM
 
 1. Install `verilator` and `sbt` as described above
-2. Change `TARGET` to `tsim` in `<tvm-root>/tvm/vta/config/vta_config.json`
-3. Build [tvm](https://docs.tvm.ai/install/from_source.html#build-the-shared-library)
+2. Build [tvm](https://docs.tvm.ai/install/from_source.html#build-the-shared-library)
 
 ## How to run VTA TSIM examples
 
-There are two sample VTA accelerators (add-by-one) designed in Chisel3 and Verilog to show how *TSIM* works.
+There are two sample VTA accelerators, add-a-constant, designed in Chisel3 and Verilog to show how *TSIM* works.
 The default `TARGET` language for these two implementations is Verilog. The following instructions show
 how to run both of them:
 
-* Verilog add-by-one
+* Test Verilog backend
     * Go to `<tvm-root>/vta/apps/tsim_example`
-    * Run `make` to build and run add-by-one test
+    * Run `make`
 
-* Chisel3 add-by-one
-    * Open `<tvm-root>/vta/apps/tsim_example/python/tsim/config.json`
-    * Change `TARGET` from `verilog` to `chisel`
-    * Go to `tvm/vta/apps/tsim_example`
-    * Run `make` to build and run add-by-one test
+* Test Chisel3 backend
+    * Open `<tvm-root>/vta/apps/tsim_example`
+    * Run `make run_chisel`
 
 * Some pointers
-    * Add-by-one test `<tvm-root>/vta/apps/tsim_example/tests/python/add_by_one.py`
-    * Add-by-one accelerator in Verilog `<tvm-root>/vta/apps/tsim_example/hardware/verilog`
-    * Add-by-one accelerator in Chisel3 `<tvm-root>/vta/apps/tsim_example/hardware/chisel`
-    * Software driver that handles the accelerator `<tvm-root>/vta/apps/tsim_example/src/driver.cc`
-    * Build cmake script for software library`<tvm-root>/vta/apps/tsim_example/cmake/modules/sw.cmake`
-    * Build cmake script for hardware library`<tvm-root>/vta/apps/tsim_example/cmake/modules/hw.cmake`
+    * Verilog and Chisel3 tests in `<tvm-root>/vta/apps/tsim_example/tests/python`
+    * Verilog accelerator backend `<tvm-root>/vta/apps/tsim_example/hardware/verilog`
+    * Chisel3 accelerator backend `<tvm-root>/vta/apps/tsim_example/hardware/chisel`
+    * Software C++ driver (backend) that handles the accelerator `<tvm-root>/vta/apps/tsim_example/src/driver.cc`
+    * Software Python driver (frontend) that handles the accelerator `<tvm-root>/vta/apps/tsim_example/python/accel`