[ARM] Support NCHWc alter layout in the fallback mode #10724
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masahi
commented
Mar 23, 2022
| @@ -101,9 +102,6 @@ def _alter_conv2d_layout(attrs, inputs, tinfos, out_type): | |||
| # we then assume it's not necessary to alter this op. | |||
| return None | |||
| cfg = dispatch_ctx.query(target, workload) | |||
| if cfg.is_fallback: # if is fallback, clear query cache and return None | |||
| autotvm.task.clear_fallback_cache(target, workload) | |||
| return None | |||
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I hope it's safe to remove this. The x86 counterpart doesn't have thing like this.
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If I can pass the CI with this change, I assume it is safe.
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@Mousius - could you please look at this given you've recently been turning on topi tests on aarch64 ?
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I need to remove this code because it always makes alter_layout nop in the fallback mode. In contrast, in the x86 schedule, alter_layout always fires.
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The CI has passed. I found that Giuseppe's im2col based conv2d implementation can fail to tensorize in the fallback mode, so I partially restored the fallback return path above.
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tkonolige
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junrushao
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Mousius
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| @@ -149,5 +151,49 @@ def extract_task_qbert(): | |||
| assert "vnni" in annotations["schedule_rule"] | |||
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| def extract_task_arm_conv2d_nchwc(): | |||
pfk-beta
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Apr 11, 2022
* [ARM] Support NCHWc alter layout in the fallback mode * remove fallback path * add test * fixed int32_lanes and add channel check * fixed schedule dispatch bug * add workaround fallback path for NHWC im2col based GEMM schedule * int32_lanes=4 by default * typo * update test
Anndrey24
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Aug 17, 2023
…ts matrix for arm_cpu NHWC quantized conv2d Fixed arm_cpu strategy bug which was causing tensorization errors when using the `AlterOpLayout` pass for the quantized NHWC conv2d schedules, as discovered in apache#10724. Therefore, we can now also enable the usage of `AlterOpLayout` for these schedules in order to transform the weight matrix at compile time, instead of runtime as before. I also modified the padding in `Conv2DGemmWeightTransformRel` and `interleave_transpose_weights` to reflect the changes made in apache#13669 and updated the AlterOpLayout tests accordingly.
lhutton1
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Aug 23, 2023
…ts matrix for arm_cpu NHWC quantized conv2d (#15584) Fixed arm_cpu strategy bug which was causing tensorization errors when using the `AlterOpLayout` pass for the quantized NHWC conv2d schedules, as discovered in #10724. Therefore, we can now also enable the usage of `AlterOpLayout` for these schedules in order to transform the weight matrix at compile time, instead of runtime as before. I also modified the padding in `Conv2DGemmWeightTransformRel` and `interleave_transpose_weights` to reflect the changes made in #13669 and updated the AlterOpLayout tests accordingly.
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I want to extract tuning tasks for ARM int8 tensorization. The current
alter_layoutcode intopi/arm_cpudoesn't fire in the fallback mode, which has been fixed in the PR.@tkonolige @comaniac