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Adding support for Hexagon User DMA Engine #10217
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#define DESC_DESCTYPE_1D 0 | ||
#define DESC_DESCTYPE_2D 1 | ||
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// TODO(Straw): Definition? Not in the spec. |
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Trying to understand what this TODO means, could you elaborate?
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Good question. The fields marked with this TODO were in header files sent by Qualcomm but the fields are not described in the spec. I left myself a TODO to investigate. Also added a "thank you" to Qualcomm in the description for sending code that was leveraged here.
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LGTM. For posterity, when you say existing tests cover this PR; which tests are we talking about?
I added a link to the test in the description. |
CC @masahi and @kparzysz-quic |
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Looks good overall.
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LGTM, thanks!
* initial hexagon user dma impl * Hexagon User DMA descriptor, instruction and register headers * Synchronous 1D DMA working * HexagonBuffer unit tests passing with memcpy * cleanup * comments and orgnanize code * format and lint * init function + other code review feedback * add ifdef hexagon around inline asm
* initial hexagon user dma impl * Hexagon User DMA descriptor, instruction and register headers * Synchronous 1D DMA working * HexagonBuffer unit tests passing with memcpy * cleanup * comments and orgnanize code * format and lint * init function + other code review feedback * add ifdef hexagon around inline asm
Adding support for the Hexagon User DMA engine consisting of three header files which describe the DMA engine in terms of its descriptors, instructions and registers. Also adding a flow for synchronous (blocking) 1D (vs. 2D) DMA which mimics memcpy semantics as a starting place for Hexagon User DMA engine support. This existing test covers this PR:
tvm/tests/python/contrib/test_hexagon/rpc/test_launcher.py
Line 81 in 2a1cc09
Many thanks to the folks at Qualcomm for sending over code which was leveraged for this PR.