hardware refactor for increased FPGA coverage, small optimizations

apache · Jul 4, 2019 · c332e94 · c332e94
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diff --git a/docs/vta/install.md b/docs/vta/install.md
@@ -187,28 +187,28 @@ This third and last guide allows users to generate custom VTA bitstreams using f
 
 ### Xilinx Toolchain Installation
 
-We recommend using `Vivado 2018.2` since our scripts have been tested to work on this version of the Xilinx toolchains.
+We recommend using `Vivado 2018.3` since our scripts have been tested to work on this version of the Xilinx toolchains.
 Our guide is written for Linux (Ubuntu) installation.
 
-You’ll need to install Xilinx’ FPGA compilation toolchain, [Vivado HL WebPACK 2018.2](https://www.xilinx.com/products/design-tools/vivado.html), which a license-free version of the Vivado HLx toolchain.
+You’ll need to install Xilinx’ FPGA compilation toolchain, [Vivado HL WebPACK 2018.3](https://www.xilinx.com/products/design-tools/vivado.html), which a license-free version of the Vivado HLx toolchain.
 
 #### Obtaining and Launching the Vivado GUI Installer
 
-1. Go to the [download webpage](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2018-2.html), and download the Linux Self Extracting Web Installer for Vivado HLx 2018.2: WebPACK and Editions.
+1. Go to the [download webpage](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2018-3.html), and download the Linux Self Extracting Web Installer for Vivado HLx 2018.3: WebPACK and Editions.
 2. You’ll have to sign in with a Xilinx account. This requires a Xilinx account creation that will take 2 minutes.
-3. Complete the Name and Address Verification by clicking “Next”, and you will get the opportunity to download a binary file, called `Xilinx_Vivado_SDK_Web_2018.2_0614_1954_Lin64.bin`.
+3. Complete the Name and Address Verification by clicking “Next”, and you will get the opportunity to download a binary file, called `Xilinx_Vivado_SDK_Web_2018.3_1207_2324_Lin64.bin`.
 4. Now that the file is downloaded, go to your `Downloads` directory, and change the file permissions so it can be executed:
 ```bash
-chmod u+x Xilinx_Vivado_SDK_Web_2018.2_0614_1954_Lin64.bin
+chmod u+x Xilinx_Vivado_SDK_Web_2018.3_1207_2324_Lin64.bin
 ```
 5. Now you can execute the binary:
 ```bash
-./Xilinx_Vivado_SDK_Web_2018.2_0614_1954_Lin64.bin
+./Xilinx_Vivado_SDK_Web_2018.3_1207_2324_Lin64.bin
 ```
 
 #### Xilinx Vivado GUI Installer Steps
 
-At this point you've launched the Vivado 2018.2 Installer GUI program.
+At this point you've launched the Vivado 2018.3 Installer GUI program.
 
 1. Click “Next” on the *Welcome* screen.
 2. On the *Select Install Type* screen, enter your Xilinx user credentials under the “User Authentication” box and select the “Download and Install Now” option before clicking “Next” .
@@ -230,8 +230,8 @@ At this point you've launched the Vivado 2018.2 Installer GUI program.
 
 The last step is to update your `~/.bashrc` with the following lines. This will include all of the Xilinx binary paths so you can launch compilation scripts from the command line.
 ```bash
-# Xilinx Vivado 2018.2 environment
-export XILINX_VIVADO=${XILINX_PATH}/Vivado/2018.2
+# Xilinx Vivado 2018.3 environment
+export XILINX_VIVADO=${XILINX_PATH}/Vivado/2018.3
 export PATH=${XILINX_VIVADO}/bin:${PATH}
 ```
 

diff --git a/vta/config/pynq_sample.json b/vta/config/pynq_sample.json
@@ -1,15 +1,20 @@
 {
   "TARGET" : "pynq",
-  "HW_FREQ" : 100,
-  "HW_CLK_TARGET" : 8,
   "HW_VER" : "0.0.0",
+  "HW_FREQ" : 100,
+  "HW_CLK_TARGET" : 7,
+  "ALU_EN" : true,
+  "MUL_EN" : false,
+  "GEMM_II" : 1,
+  "TALU_II" : 2,
   "LOG_INP_WIDTH" : 3,
   "LOG_WGT_WIDTH" : 3,
   "LOG_ACC_WIDTH" : 5,
   "LOG_OUT_WIDTH" : 3,
   "LOG_BATCH" : 0,
   "LOG_BLOCK_IN" : 4,
   "LOG_BLOCK_OUT" : 4,
+  "LOG_BUS_WIDTH" : 6,
   "LOG_UOP_BUFF_SIZE" : 15,
   "LOG_INP_BUFF_SIZE" : 15,
   "LOG_WGT_BUFF_SIZE" : 18,

diff --git a/vta/config/vta_config.json b/vta/config/vta_config.json
@@ -1,15 +1,20 @@
 {
   "TARGET" : "sim",
+  "HW_VER" : "0.0.0",
   "HW_FREQ" : 100,
   "HW_CLK_TARGET" : 7,
-  "HW_VER" : "0.0.0",
+  "ALU_EN" : true,
+  "MUL_EN" : false,
+  "GEMM_II" : 1,
+  "TALU_II" : 2,
   "LOG_INP_WIDTH" : 3,
   "LOG_WGT_WIDTH" : 3,
   "LOG_ACC_WIDTH" : 5,
   "LOG_OUT_WIDTH" : 3,
   "LOG_BATCH" : 0,
   "LOG_BLOCK_IN" : 4,
   "LOG_BLOCK_OUT" : 4,
+  "LOG_BUS_WIDTH" : 6,
   "LOG_UOP_BUFF_SIZE" : 15,
   "LOG_INP_BUFF_SIZE" : 15,
   "LOG_WGT_BUFF_SIZE" : 18,

diff --git a/vta/config/vta_config.py b/vta/config/vta_config.py
@@ -54,6 +54,14 @@ def main():
                         help="print the target")
     parser.add_argument("--cfg-str", action="store_true",
                         help="print the configuration string")
+    parser.add_argument("--get-aluen", action="store_true",
+                        help="returns whether ALU is enabled")
+    parser.add_argument("--get-mulen", action="store_true",
+                        help="returns whether mul in ALU is enabled")
+    parser.add_argument("--get-gemmii", action="store_true",
+                        help="returns the GEMM core II")
+    parser.add_argument("--get-taluii", action="store_true",
+                        help="returns the tensor ALU core II")
     parser.add_argument("--get-inpwidth", action="store_true",
                         help="returns log of input bitwidth")
     parser.add_argument("--get-wgtwidth", action="store_true",
@@ -68,6 +76,8 @@ def main():
                         help="returns log of tensor block in dimension")
     parser.add_argument("--get-blockout", action="store_true",
                         help="returns log of tensor block out dimension")
+    parser.add_argument("--get-buswidth", action="store_true",
+                        help="returns log of bus width in b")
     parser.add_argument("--get-uopbuffsize", action="store_true",
                         help="returns log of micro-op buffer size in B")
     parser.add_argument("--get-inpbuffsize", action="store_true",
@@ -103,9 +113,31 @@ def main():
         raise RuntimeError("Cannot find config in %s" % str(path_list))
     cfg = json.load(open(ok_path_list[0]))
     cfg["LOG_OUT_BUFF_SIZE"] = (
-        cfg["LOG_ACC_BUFF_SIZE"] +
-        cfg["LOG_OUT_WIDTH"] -
-        cfg["LOG_ACC_WIDTH"])
+        cfg["LOG_ACC_BUFF_SIZE"] 
+        + cfg["LOG_OUT_WIDTH"]
+        - cfg["LOG_ACC_WIDTH"]) 
+    # Generate bitstream config string.
+    # Needs to match the BITSTREAM string in python/vta/environment.py
+    cfg["BITSTREAM"] = "{}_{}x{}x{}_a{}w{}o{}s{}_{}_{}_{}_{}_{}MHz_{}ns_gii{}".format(
+        cfg["TARGET"],
+        (1 << cfg["LOG_BATCH"]),
+        (1 << cfg["LOG_BLOCK_IN"]),
+        (1 << cfg["LOG_BLOCK_OUT"]),
+        (1 << cfg["LOG_INP_WIDTH"]),
+        (1 << cfg["LOG_WGT_WIDTH"]),
+        (1 << cfg["LOG_OUT_WIDTH"]),
+        (1 << cfg["LOG_ACC_WIDTH"]),
+        cfg["LOG_UOP_BUFF_SIZE"],
+        cfg["LOG_INP_BUFF_SIZE"],
+        cfg["LOG_WGT_BUFF_SIZE"],
+        cfg["LOG_ACC_BUFF_SIZE"],
+        cfg["HW_FREQ"],
+        cfg["HW_CLK_TARGET"],
+        cfg["GEMM_II"])
+    if cfg["ALU_EN"]:
+        cfg["BITSTREAM"] += "_aii{}".format(cfg["TALU_II"])
+    if cfg["MUL_EN"] and cfg["ALU_EN"]:
+        cfg["BITSTREAM"] += "_mul"
     pkg = get_pkg_config(cfg)
 
     if args.target:
@@ -121,6 +153,8 @@ def main():
         cflags_str = " ".join(pkg.cflags)
         if cfg["TARGET"] == "pynq":
             cflags_str += " -DVTA_TARGET_PYNQ"
+        if cfg["TARGET"] == "ultra96":
+            cflags_str += " -DVTA_TARGET_ULTRA96"
         print(cflags_str)
 
     if args.ldflags:
@@ -134,21 +168,19 @@ def main():
             fo.write(pkg.cfg_json)
 
     if args.cfg_str:
-        # Needs to match the BITSTREAM string in python/vta/environment.py
-        cfg_str = "{}x{}x{}_{}bx{}b_{}_{}_{}_{}_{}MHz_{}ns_v{}".format(
-            (1 << cfg["LOG_BATCH"]),
-            (1 << cfg["LOG_BLOCK_IN"]),
-            (1 << cfg["LOG_BLOCK_OUT"]),
-            (1 << cfg["LOG_INP_WIDTH"]),
-            (1 << cfg["LOG_WGT_WIDTH"]),
-            cfg["LOG_UOP_BUFF_SIZE"],
-            cfg["LOG_INP_BUFF_SIZE"],
-            cfg["LOG_WGT_BUFF_SIZE"],
-            cfg["LOG_ACC_BUFF_SIZE"],
-            cfg["HW_FREQ"],
-            cfg["HW_CLK_TARGET"],
-            cfg["HW_VER"].replace('.', '_'))
-        print(cfg_str)
+        print(cfg["BITSTREAM"])
+
+    if args.get_aluen:
+        print(cfg["ALU_EN"])
+
+    if args.get_mulen:
+        print(cfg["MUL_EN"])
+
+    if args.get_gemmii:
+        print(cfg["GEMM_II"])
+
+    if args.get_taluii:
+        print(cfg["TALU_II"])
 
     if args.get_inpwidth:
         print(cfg["LOG_INP_WIDTH"])
@@ -171,6 +203,9 @@ def main():
     if args.get_blockout:
         print(cfg["LOG_BLOCK_OUT"])
 
+    if args.get_buswidth:
+        print(cfg["LOG_BUS_WIDTH"])
+
     if args.get_uopbuffsize:
         print(cfg["LOG_UOP_BUFF_SIZE"])
 

diff --git a/vta/hardware/xilinx/Makefile b/vta/hardware/xilinx/Makefile
@@ -31,18 +31,14 @@ VIVADO = vivado
 HSI = hsi
 
 # HLS mode
-MODE = skip_sim
+MODE = all
 # Debug flag
-DEBUG = false
+DEBUG = False
 # SLURM
-SLURM = false
-# Prevent generation of DSP
-NO_DSP = false
-# Prevent generation of ALU
-NO_ALU = false
+SLURM = False
 
 # Process VTA JSON config
-VTA_CONFIG = python $(CURDIR)/../../config/vta_config.py
+VTA_CONFIG := python $(CURDIR)/../../config/vta_config.py
 CFLAGS := $(shell ${VTA_CONFIG} --cflags)
 VTA_TARGET := $(shell ${VTA_CONFIG} --target)
 
@@ -56,17 +52,22 @@ VTA_OUT_WIDTH := $(shell ${VTA_CONFIG} --get-outwidth)
 VTA_BATCH := $(shell ${VTA_CONFIG} --get-batch)
 VTA_IN_BLOCK := $(shell ${VTA_CONFIG} --get-blockin)
 VTA_OUT_BLOCK := $(shell ${VTA_CONFIG} --get-blockout)
+VTA_BUS_WIDTH := $(shell ${VTA_CONFIG} --get-buswidth)
 VTA_UOP_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-uopbuffsize)
 VTA_INP_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-inpbuffsize)
 VTA_WGT_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-wgtbuffsize)
 VTA_ACC_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-accbuffsize)
 VTA_OUT_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-outbuffsize)
+VTA_ALU_EN := $(shell ${VTA_CONFIG} --get-aluen)
+VTA_MUL_EN := $(shell ${VTA_CONFIG} --get-mulen)
 
 #---------------------
 # FPGA Parameters
 #--------------------
-VTA_CLOCK_FREQ = $(shell ${VTA_CONFIG} --get-fpgafreq)
-VTA_TARGET_PER = $(shell ${VTA_CONFIG} --get-fpgaper)
+VTA_CLOCK_FREQ := $(shell ${VTA_CONFIG} --get-fpgafreq)
+VTA_TARGET_PER := $(shell ${VTA_CONFIG} --get-fpgaper)
+VTA_GEMM_II := $(shell ${VTA_CONFIG} --get-gemmii)
+VTA_TALU_II := $(shell ${VTA_CONFIG} --get-taluii)
 
 #---------------------
 # Compilation parameters
@@ -76,20 +77,21 @@ VTA_TARGET_PER = $(shell ${VTA_CONFIG} --get-fpgaper)
 VTA_HW_COMP_THREADS = 8
 
 # Derive config name
-CONF = $(shell ${VTA_CONFIG} --cfg-str)
-IP_BUILD_PATH = $(BUILD_DIR)/hls/$(CONF)
-HW_BUILD_PATH = $(BUILD_DIR)/vivado/$(CONF)
+CONF := $(shell ${VTA_CONFIG} --cfg-str)
+IP_BUILD_PATH := $(BUILD_DIR)/hls/$(CONF)
+HW_BUILD_PATH := $(BUILD_DIR)/vivado/$(CONF)
 
-ifeq ($(SLURM), true)
+# Build on local scratch drive when using cluster
+ifeq ($(SLURM), True)
 	IP_BUILD_PATH = /scratch/hls/$(CONF)
 	HW_BUILD_PATH = /scratch/vivado/$(CONF)
 endif
 
 # IP file path
-IP_PATH = $(BUILD_DIR)/hls/$(CONF)/solution0/impl/ip/xilinx_com_hls_vta_1_0.zip
+IP_PATH := $(BUILD_DIR)/hls/$(CONF)/vta_compute/solution0/impl/ip/xilinx_com_hls_compute_1_0.zip
 
 # Bitstream file path
-BIT_PATH = $(BUILD_DIR)/vivado/$(CONF)/export/$(CONF).bit
+BIT_PATH := $(BUILD_DIR)/vivado/$(CONF)/export/$(CONF).bit
 
 .PHONY: all ip bit bsp clean clean_all
 
@@ -101,13 +103,15 @@ $(IP_PATH): $(SRC_DIR)/*
 	mkdir -p $(IP_BUILD_PATH)
 	cd $(IP_BUILD_PATH) && \
 		$(VIVADO_HLS) -f $(SCRIPT_DIR)/hls.tcl \
-		-tclargs $(SRC_DIR) $(SIM_DIR) $(TEST_DIR) $(INCLUDE_DIR) \
-		$(MODE) $(DEBUG) $(NO_DSP) $(NO_ALU) $(VTA_TARGET_PER) \
+		-tclargs $(VTA_TARGET) \
+		$(SRC_DIR) $(SIM_DIR) $(TEST_DIR) $(INCLUDE_DIR) \
+		$(MODE) $(DEBUG) $(VTA_ALU_EN) $(VTA_MUL_EN) \
+		$(VTA_TARGET_PER) $(VTA_GEMM_II) $(VTA_TALU_II) \
 		$(VTA_INP_WIDTH) $(VTA_WGT_WIDTH) $(VTA_ACC_WIDTH) $(VTA_OUT_WIDTH) \
-		$(VTA_BATCH) $(VTA_IN_BLOCK) $(VTA_OUT_BLOCK) \
+		$(VTA_BATCH) $(VTA_IN_BLOCK) $(VTA_OUT_BLOCK) $(VTA_BUS_WIDTH) \
 		$(VTA_UOP_BUFF_SIZE) $(VTA_INP_BUFF_SIZE) $(VTA_WGT_BUFF_SIZE) \
 		$(VTA_ACC_BUFF_SIZE) $(VTA_OUT_BUFF_SIZE)
-ifeq ($(SLURM), true)
+ifeq ($(SLURM), True)
 	mkdir -p $(BUILD_DIR)/hls
 	mv $(IP_BUILD_PATH) $(BUILD_DIR)/hls/.
 endif
@@ -116,11 +120,12 @@ $(BIT_PATH): $(IP_PATH)
 	mkdir -p $(HW_BUILD_PATH)
 	cd $(HW_BUILD_PATH) && \
 		$(VIVADO) -mode tcl -source $(SCRIPT_DIR)/vivado.tcl \
-		-tclargs $(BUILD_DIR)/hls/$(CONF) $(VTA_HW_COMP_THREADS) $(VTA_CLOCK_FREQ) \
+		-tclargs $(VTA_TARGET) $(BUILD_DIR)/hls/$(CONF) $(VTA_HW_COMP_THREADS) \
+		$(VTA_CLOCK_FREQ) $(VTA_GEMM_II) \
 		$(VTA_INP_WIDTH) $(VTA_WGT_WIDTH) $(VTA_OUT_WIDTH) \
 		$(VTA_BATCH) $(VTA_IN_BLOCK) $(VTA_OUT_BLOCK) \
 		$(VTA_INP_BUFF_SIZE) $(VTA_WGT_BUFF_SIZE) $(VTA_OUT_BUFF_SIZE)
-ifeq ($(SLURM), true)
+ifeq ($(SLURM), True)
 	mkdir -p $(BUILD_DIR)/vivado
 	mv $(HW_BUILD_PATH) $(BUILD_DIR)/vivado/.
 endif