[VTA] HW sources refactor (#5188)

* refactor

* path udpate

.gitmodules

@@ -7,3 +7,6 @@
 [submodule "3rdparty/rang"]
 	path = 3rdparty/rang
 	url = https://github.com/agauniyal/rang
+[submodule "3rdparty/vta-hw"]
+	path = 3rdparty/vta-hw
+	url = https://github.com/apache/incubator-tvm-vta

Makefile

@@ -29,7 +29,7 @@ ifndef DLPACK_PATH
 endif
 
 ifndef VTA_HW_PATH
-  VTA_HW_PATH = $(ROOTDIR)/vta/vta-hw
+  VTA_HW_PATH = $(ROOTDIR)/3rdparty/vta-hw
 endif
 
 INCLUDE_FLAGS = -Iinclude -I$(DLPACK_PATH)/include -I$(DMLC_CORE_PATH)/include

cmake/modules/VTA.cmake

@@ -20,7 +20,7 @@ find_program(PYTHON NAMES python python3 python3.6)
 
 # Throw error if VTA_HW_PATH is not set
 if(NOT DEFINED ENV{VTA_HW_PATH})
-  set(VTA_HW_PATH ${CMAKE_CURRENT_SOURCE_DIR}/vta/vta-hw)
+  set(VTA_HW_PATH ${CMAKE_CURRENT_SOURCE_DIR}/3rdparty/vta-hw)
 else()
   set(VTA_HW_PATH $ENV{VTA_HW_PATH})
 endif()

docs/vta/dev/config.rst

@@ -21,7 +21,7 @@ VTA Configuration
 The VTA stack incorporates both a hardware accelerator stack and
 a TVM based software stack.
 VTA incorporates flexibility out of the box: by modifying the
-``vta/vta-hw/config/vta_config.json`` high-level configuration file,
+``3rdparty/vta-hw/config/vta_config.json`` high-level configuration file,
 the user can change the shape of the tensor intrinsic,
 clock frequency, pipelining, data type width, and on-chip buffer sizes.
 

docs/vta/dev/hardware.rst

@@ -53,17 +53,17 @@ HLS Hardware Source Organization
 
 The VTA design is currently specified in Vivado HLS C++, which is only supported
 by Xilinx toolchains.
-The VTA hardware sources are contained under ``vta/vta-hw/hardware/xilinx/sources``:
+The VTA hardware sources are contained under ``3rdparty/vta-hw/hardware/xilinx/sources``:
 
  - ``vta.cc`` contains the definitions for each VTA module, as well as a top
    level behavioral model for the top-level VTA design.
  - ``vta.h`` contains type definitions using Xilinx ``ap_int`` types, and
    function prototypes declarations.
 
-In addition preprocessor macros are defined under ``vta/vta-hw/include/vta/hw_spec.h``.
+In addition preprocessor macros are defined under ``3rdparty/vta-hw/include/vta/hw_spec.h``.
 Much of these macro definitions are derived from the parameters listed in the
-``vta/vta-hw/config/vta_config.json`` file.
-The json file is processed by ``vta/vta-hw/config/vta_config.py`` to produce a string of
+``3rdparty/vta-hw/config/vta_config.json`` file.
+The json file is processed by ``3rdparty/vta-hw/config/vta_config.py`` to produce a string of
 compile flags that define the preprocessor macros.
 That string is used by the makefile in order to set those high-level
 parameters in both the HLS hardware synthesis compiler, and the C++
@@ -220,7 +220,7 @@ Microarchitectural Overview
 ---------------------------
 
 We describe the modules that compose the VTA design.
-The module definitions are contained in ``vta/vta-hw/hardware/xilinx/sources/vta.cc``.
+The module definitions are contained in ``3rdparty/vta-hw/hardware/xilinx/sources/vta.cc``.
 
 Fetch Module
 ~~~~~~~~~~~~

docs/vta/install.md

@@ -32,7 +32,7 @@ For a quick and easy start, checkout the [Docker Guide](https://tvm.apache.org/d
 You'll need to set the following paths to use VTA:
 ```bash
 export TVM_PATH=<path to TVM root>
-export VTA_HW_PATH=$TVM_PATH/vta/vta-hw
+export VTA_HW_PATH=$TVM_PATH/3rdparty/vta-hw
 ```
 
 The VTA functional simulation library needs to be enabled when building TVM.
@@ -66,7 +66,7 @@ You are invited to try out our [VTA programming tutorials](https://tvm.apache.or
 ### Advanced Configuration (optional)
 
 VTA is a generic configurable deep learning accelerator.
-The configuration is specified by `vta_config.json` under `vta/vta-hw/config`.
+The configuration is specified by `vta_config.json` under `3rdparty/vta-hw/config`.
 This file provides an architectural specification of the VTA accelerator to parameterize the TVM compiler stack and the VTA hardware stack.
 
 The VTA configuration file also specifies the TVM compiler target.
@@ -76,7 +76,7 @@ To do so,
 
 ```bash
 cd <tvm root>
-vim vta/vta-hw/config/vta_config.json
+vim 3rdparty/vta-hw/config/vta_config.json
 # edit vta_config.json
 make
 ```
@@ -134,7 +134,7 @@ mkdir build
 cp cmake/config.cmake build/.
 echo 'set(USE_VTA_FPGA ON)' >> build/config.cmake
 # Copy pynq specific configuration
-cp vta/vta-hw/config/pynq_sample.json vta/vta-hw/config/vta_config.json
+cp 3rdparty/vta-hw/config/pynq_sample.json 3rdparty/vta-hw/config/vta_config.json
 cd build
 cmake ..
 make runtime vta -j2
@@ -168,7 +168,7 @@ In addition, you'll need to edit the `vta_config.json` file on the host to indic
 ```bash
 # On the Host-side
 cd <tvm root>
-cp vta/vta-hw/config/pynq_sample.json vta/vta-hw/config/vta_config.json
+cp 3rdparty/vta-hw/config/pynq_sample.json 3rdparty/vta-hw/config/vta_config.json
 ```
 
 This time again, we will run the 2D convolution testbench.
@@ -359,19 +359,19 @@ For this custom VTA bitstream compilation exercise, we'll change the frequency o
 * Set the `HW_FREQ` field to `142`. The Pynq board supports 100, 142, 167 and 200MHz clocks. Note that the higher the frequency, the harder it will be to close timing. Increasing the frequency can lead to timing violation and thus faulty hardware execution.
 * Set the `HW_CLK_TARGET` to `6`. This parameters refers to the target clock period in nano seconds for HLS - a lower clock period leads to more aggressive pipelining to achieve timing closure at higher frequencies. Technically a 142MHz clock would require a 7ns target, but we intentionally lower the clock target to 6ns to more aggressively pipeline our design.
 
-Bitstream generation is driven by a top-level `Makefile` under `<tvm root>/vta/vta-hw/hardware/xilinx/`.
+Bitstream generation is driven by a top-level `Makefile` under `<tvm root>/3rdparty/vta-hw/hardware/xilinx/`.
 
 If you just want to simulate the VTA design in software emulation to make sure that it is functional, enter:
 ```bash
-cd <tvm root>/vta/vta-hw/hardware/xilinx
+cd <tvm root>/3rdparty/vta-hw/hardware/xilinx
 make ip MODE=sim
 ```
 
 If you just want to generate the HLS-based VTA IP cores without launching the entire design place and route, enter:
 ```bash
 make ip
 ```
-You'll be able to view the HLS synthesis reports under `<tvm root>/vta/vta-hw/build/hardware/xilinx/hls/` `<configuration>/<block>/solution0/syn/report/<block>_csynth.rpt`
+You'll be able to view the HLS synthesis reports under `<tvm root>/3rdparty/vta-hw/build/hardware/xilinx/hls/` `<configuration>/<block>/solution0/syn/report/<block>_csynth.rpt`
 > Note: The `<configuration>` name is a string that summarizes the VTA configuration parameters listed in the `vta_config.json`. The `<block>` name refers to the specific module (or HLS function) that compose the high-level VTA pipeline.
 
 Finally to run the full hardware compilation and generate the VTA bitstream, run:
@@ -383,20 +383,20 @@ make
 This process is lengthy, and can take around up to an hour to complete depending on your machine's specs.
 We recommend setting the `VTA_HW_COMP_THREADS` variable in the Makefile to take full advantage of all the cores on your development machine.
 
-Once the compilation completes, the generated bitstream can be found under `<tvm root>/vta/vta-hw/build/hardware/xilinx/vivado/<configuration>/export/vta.bit`.
+Once the compilation completes, the generated bitstream can be found under `<tvm root>/3rdparty/vta-hw/build/hardware/xilinx/vivado/<configuration>/export/vta.bit`.
 
 ### Chisel-based Custom VTA Bitstream Compilation for DE10-Nano
 
-Similar to the HLS-based design, high-level hardware parameters in Chisel-based design are listed in the VTA configuration file [Configs.scala](https://github.com/apache/incubator-tvm/blob/master/vta/vta-hw/hardware/chisel/src/main/scala/core/Configs.scala), and they can be customized by the user.
+Similar to the HLS-based design, high-level hardware parameters in Chisel-based design are listed in the VTA configuration file [Configs.scala](https://github.com/apache/incubator-tvm/blob/master/3rdparty/vta-hw/hardware/chisel/src/main/scala/core/Configs.scala), and they can be customized by the user.
 
-For Intel FPGA, bitstream generation is driven by a top-level `Makefile` under `<tvmroot>/vta/vta-hw/hardware/intel`.
+For Intel FPGA, bitstream generation is driven by a top-level `Makefile` under `<tvm root>/3rdparty/vta-hw/hardware/intel`.
 
 If you just want to generate the Chisel-based VTA IP core for the DE10-Nano board without compiling the design for the FPGA hardware, enter:
 ```bash
-cd <tvmroot>/vta/vta-hw/hardware/intel
+cd <tvm root>/3rdparty/vta-hw/hardware/intel
 make ip
 ```
-Then you'll be able to locate the generated verilog file at `<tvmroot>/vta/vta-hw/build/hardware/intel/chisel/<configuration>/VTA.DefaultDe10Config.v`.
+Then you'll be able to locate the generated verilog file at `<tvm root>/3rdparty/vta-hw/build/hardware/intel/chisel/<configuration>/VTA.DefaultDe10Config.v`.
 
 If you would like to run the full hardware compilation for the `de10nano` board:
 ```bash
@@ -405,14 +405,14 @@ make
 
 This process might be a bit lengthy, and might take up to half an hour to complete depending on the performance of your PC. The Quartus Prime software would automatically detect the number of cores available on your PC and try to utilize all of them to perform such process.
 
-Once the compilation completes, the generated bistream can be found under `<tvmroot>vtay/vta-hw/build/hardware/intel/quartus/<configuration>/export/vta.rbf`. You can also open the Quartus project file (.qpf) available at `<tvmroot>/vta/vta-hw/build/hardware/intel/quartus/<configuration>/de10_nano_top.qpf` to look around the generated reports.
+Once the compilation completes, the generated bistream can be found under `<tvm root>/3rdparty/vta-hw/build/hardware/intel/quartus/<configuration>/export/vta.rbf`. You can also open the Quartus project file (.qpf) available at `<tvm root>/3rdparty/vta-hw/build/hardware/intel/quartus/<configuration>/de10_nano_top.qpf` to look around the generated reports.
 
 ### Use the Custom Bitstream
 
 We can program the new VTA FPGA bitstream by setting the bitstream path of the `vta.program_fpga()` function in the tutorial examples, or in the `test_program_rpc.py` script.
 
 ```python
-vta.program_fpga(remote, bitstream="<tvm root>/vta/vta-hw/build/hardware/xilinx/vivado/<configuration>/export/vta.bit")
+vta.program_fpga(remote, bitstream="<tvm root>/3rdparty/vta-hw/build/hardware/xilinx/vivado/<configuration>/export/vta.bit")
 ```
 
 Instead of downloading a pre-built bitstream from the VTA bitstream repository, TVM will instead use the new bitstream you just generated, which is a VTA design clocked at a higher frequency.

tests/scripts/task_build.sh

@@ -15,4 +15,5 @@
 # KIND, either express or implied.  See the License for the
 # specific language governing permissions and limitations
 # under the License.
+export VTA_HW_PATH=`pwd`/3rdparty/vta-hw
 cd $1 && cmake .. && make $2 && cd ..

tests/scripts/task_cpp_unittest.sh

@@ -20,6 +20,8 @@ set -e
 set -u
 
 export LD_LIBRARY_PATH="lib:${LD_LIBRARY_PATH:-}"
+# NOTE: important to use abspath, when VTA is enabled.
+export VTA_HW_PATH=`pwd`/3rdparty/vta-hw
 
 # Remove existing testcases
 rm -f build/*_test

tests/scripts/task_python_vta_fsim.sh

@@ -21,7 +21,7 @@ set -u
 
 export TVM_PATH=`pwd`
 export PYTHONPATH=${TVM_PATH}/python:${TVM_PATH}/vta/python:${TVM_PATH}/topi/python
-export VTA_HW_PATH=`pwd`/vta/vta-hw
+export VTA_HW_PATH=`pwd`/3rdparty/vta-hw
 
 # cleanup pycache
 find . -type f -path "*.pyc" | xargs rm -f

tests/scripts/task_python_vta_tsim.sh

@@ -21,7 +21,7 @@ set -u
 
 export TVM_PATH=`pwd`
 export PYTHONPATH=${TVM_PATH}/python:${TVM_PATH}/vta/python:${TVM_PATH}/topi/python
-export VTA_HW_PATH=`pwd`/vta/vta-hw
+export VTA_HW_PATH=`pwd`/3rdparty/vta-hw
 
 # cleanup pycache
 find . -type f -path "*.pyc" | xargs rm -f

vta/python/vta/environment.py

@@ -28,7 +28,7 @@
 def get_vta_hw_path():
     """Get the VTA HW path."""
     curr_path = os.path.dirname(os.path.abspath(os.path.expanduser(__file__)))
-    vta_hw_default = os.path.abspath(os.path.join(curr_path, "../../vta-hw"))
+    vta_hw_default = os.path.abspath(os.path.join(curr_path, "../../../3rdparty/vta-hw"))
     VTA_HW_PATH = os.getenv('VTA_HW_PATH', vta_hw_default)
     return os.path.abspath(VTA_HW_PATH)
 

vta/tutorials/autotvm/tune_relay_vta.py

@@ -181,7 +181,7 @@ def compile_network(env, target, model, start_pack, stop_pack):
 tracker_host = os.environ.get("TVM_TRACKER_HOST", '0.0.0.0')
 tracker_port = int(os.environ.get("TVM_TRACKER_PORT", 9190))
 
-# Load VTA parameters from the vta/vta-hw/config/vta_config.json file
+# Load VTA parameters from the 3rdparty/vta-hw/config/vta_config.json file
 env = vta.get_env()
 
 # This target is used for cross compilation. You can query it by :code:`gcc -v` on your device.

vta/tutorials/frontend/deploy_classification.py

@@ -68,7 +68,7 @@
 # -------------------------------------
 # Execute on CPU vs. VTA, and define the model.
 
-# Load VTA parameters from the vta/vta-hw/config/vta_config.json file
+# Load VTA parameters from the 3rdparty/vta-hw/config/vta_config.json file
 env = vta.get_env()
 
 # Set ``device=arm_cpu`` to run inference on the CPU

vta/tutorials/frontend/deploy_detection.py

@@ -111,7 +111,7 @@
 # --------------------------------------
 # Execute on CPU vs. VTA, and define the model.
 
-# Load VTA parameters from the vta/vta-hw/config/vta_config.json file
+# Load VTA parameters from the 3rdparty/vta-hw/config/vta_config.json file
 env = vta.get_env()
 # Set ``device=arm_cpu`` to run inference on the CPU
 # or ``device=vta`` to run inference on the FPGA.

vta/tutorials/matrix_multiply.py

@@ -43,7 +43,7 @@
 from tvm.contrib import util
 from vta.testing import simulator
 
-# Load VTA parameters from the vta/vta-hw/config/vta_config.json file
+# Load VTA parameters from the 3rdparty/vta-hw/config/vta_config.json file
 env = vta.get_env()
 
 # We read the Pynq RPC host IP address and port number from the OS environment

vta/tutorials/optimize/convolution_opt.py

@@ -47,7 +47,7 @@
 from tvm.contrib import util
 from vta.testing import simulator
 
-# Load VTA parameters from the vta/vta-hw/config/vta_config.json file
+# Load VTA parameters from the 3rdparty/vta-hw/config/vta_config.json file
 env = vta.get_env()
 
 # We read the Pynq RPC host IP address and port number from the OS environment

vta/tutorials/optimize/matrix_multiply_opt.py

@@ -46,7 +46,7 @@
 from tvm.contrib import util
 from vta.testing import simulator
 
-# Load VTA parameters from the vta/vta-hw/config/vta_config.json file
+# Load VTA parameters from the 3rdparty/vta-hw/config/vta_config.json file
 env = vta.get_env()
 
 # We read the Pynq RPC host IP address and port number from the OS environment