cleaning up parameters that won't be needed for now

apache · Jul 4, 2019 · 0755361 · 0755361
1 parent ea2d503
commit 0755361
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Showing 8 changed files with 151 additions and 240 deletions.
diff --git a/vta/config/pynq_sample.json b/vta/config/pynq_sample.json
@@ -1,12 +1,8 @@
 {
-  "TARGET" : "pynq",
+  "TARGET" : "sim",
   "HW_VER" : "0.0.0",
   "HW_FREQ" : 100,
   "HW_CLK_TARGET" : 7,
-  "ALU_EN" : true,
-  "MUL_EN" : false,
-  "GEMM_II" : 1,
-  "TALU_II" : 2,
   "LOG_INP_WIDTH" : 3,
   "LOG_WGT_WIDTH" : 3,
   "LOG_ACC_WIDTH" : 5,
@@ -16,7 +12,7 @@
   "LOG_BLOCK_OUT" : 4,
   "LOG_BUS_WIDTH" : 6,
   "LOG_UOP_BUFF_SIZE" : 15,
-  "LOG_INP_BUFF_SIZE" : 15,
+  "LOG_INP_BUFF_SIZE" :15,
   "LOG_WGT_BUFF_SIZE" : 18,
   "LOG_ACC_BUFF_SIZE" : 17
 }
diff --git a/vta/config/vta_config.json b/vta/config/vta_config.json
@@ -1,12 +1,8 @@
 {
-  "TARGET" : "sim",
+  "TARGET" : "pynq",
   "HW_VER" : "0.0.0",
   "HW_FREQ" : 100,
   "HW_CLK_TARGET" : 7,
-  "ALU_EN" : true,
-  "MUL_EN" : false,
-  "GEMM_II" : 1,
-  "TALU_II" : 2,
   "LOG_INP_WIDTH" : 3,
   "LOG_WGT_WIDTH" : 3,
   "LOG_ACC_WIDTH" : 5,
@@ -16,7 +12,7 @@
   "LOG_BLOCK_OUT" : 4,
   "LOG_BUS_WIDTH" : 6,
   "LOG_UOP_BUFF_SIZE" : 15,
-  "LOG_INP_BUFF_SIZE" : 15,
+  "LOG_INP_BUFF_SIZE" :15,
   "LOG_WGT_BUFF_SIZE" : 18,
   "LOG_ACC_BUFF_SIZE" : 17
 }
diff --git a/vta/config/vta_config.py b/vta/config/vta_config.py
@@ -54,14 +54,6 @@ def main():
                         help="print the target")
     parser.add_argument("--cfg-str", action="store_true",
                         help="print the configuration string")
-    parser.add_argument("--get-aluen", action="store_true",
-                        help="returns whether ALU is enabled")
-    parser.add_argument("--get-mulen", action="store_true",
-                        help="returns whether mul in ALU is enabled")
-    parser.add_argument("--get-gemmii", action="store_true",
-                        help="returns the GEMM core II")
-    parser.add_argument("--get-taluii", action="store_true",
-                        help="returns the tensor ALU core II")
     parser.add_argument("--get-inpwidth", action="store_true",
                         help="returns log of input bitwidth")
     parser.add_argument("--get-wgtwidth", action="store_true",
@@ -118,7 +110,7 @@ def main():
         - cfg["LOG_ACC_WIDTH"]) 
     # Generate bitstream config string.
     # Needs to match the BITSTREAM string in python/vta/environment.py
-    cfg["BITSTREAM"] = "{}_{}x{}x{}_a{}w{}o{}s{}_{}_{}_{}_{}_{}MHz_{}ns_gii{}".format(
+    cfg["BITSTREAM"] = "{}_{}x{}x{}_a{}w{}o{}s{}_{}_{}_{}_{}_{}MHz_{}ns".format(
         cfg["TARGET"],
         (1 << cfg["LOG_BATCH"]),
         (1 << cfg["LOG_BLOCK_IN"]),
@@ -132,12 +124,7 @@ def main():
         cfg["LOG_WGT_BUFF_SIZE"],
         cfg["LOG_ACC_BUFF_SIZE"],
         cfg["HW_FREQ"],
-        cfg["HW_CLK_TARGET"],
-        cfg["GEMM_II"])
-    if cfg["ALU_EN"]:
-        cfg["BITSTREAM"] += "_aii{}".format(cfg["TALU_II"])
-    if cfg["MUL_EN"] and cfg["ALU_EN"]:
-        cfg["BITSTREAM"] += "_mul"
+        cfg["HW_CLK_TARGET"])
     pkg = get_pkg_config(cfg)
 
     if args.target:
@@ -170,18 +157,6 @@ def main():
     if args.cfg_str:
         print(cfg["BITSTREAM"])
 
-    if args.get_aluen:
-        print(cfg["ALU_EN"])
-
-    if args.get_mulen:
-        print(cfg["MUL_EN"])
-
-    if args.get_gemmii:
-        print(cfg["GEMM_II"])
-
-    if args.get_taluii:
-        print(cfg["TALU_II"])
-
     if args.get_inpwidth:
         print(cfg["LOG_INP_WIDTH"])
 

diff --git a/vta/hardware/xilinx/Makefile b/vta/hardware/xilinx/Makefile
@@ -28,18 +28,9 @@ INCLUDE_DIR = $(ROOTDIR)/../../include
 # Executables
 VIVADO_HLS = vivado_hls
 VIVADO = vivado
-HSI = hsi
-
-# HLS mode
-MODE = all
-# Debug flag
-DEBUG = False
-# SLURM
-SLURM = False
 
 # Process VTA JSON config
 VTA_CONFIG := python $(CURDIR)/../../config/vta_config.py
-CFLAGS := $(shell ${VTA_CONFIG} --cflags)
 VTA_TARGET := $(shell ${VTA_CONFIG} --target)
 
 #---------------------
@@ -58,16 +49,12 @@ VTA_INP_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-inpbuffsize)
 VTA_WGT_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-wgtbuffsize)
 VTA_ACC_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-accbuffsize)
 VTA_OUT_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-outbuffsize)
-VTA_ALU_EN := $(shell ${VTA_CONFIG} --get-aluen)
-VTA_MUL_EN := $(shell ${VTA_CONFIG} --get-mulen)
 
 #---------------------
 # FPGA Parameters
 #--------------------
 VTA_CLOCK_FREQ := $(shell ${VTA_CONFIG} --get-fpgafreq)
 VTA_TARGET_PER := $(shell ${VTA_CONFIG} --get-fpgaper)
-VTA_GEMM_II := $(shell ${VTA_CONFIG} --get-gemmii)
-VTA_TALU_II := $(shell ${VTA_CONFIG} --get-taluii)
 
 #---------------------
 # Compilation parameters
@@ -81,19 +68,13 @@ CONF := $(shell ${VTA_CONFIG} --cfg-str)
 IP_BUILD_PATH := $(BUILD_DIR)/hls/$(CONF)
 HW_BUILD_PATH := $(BUILD_DIR)/vivado/$(CONF)
 
-# Build on local scratch drive when using cluster
-ifeq ($(SLURM), True)
-	IP_BUILD_PATH = /scratch/hls/$(CONF)
-	HW_BUILD_PATH = /scratch/vivado/$(CONF)
-endif
-
 # IP file path
 IP_PATH := $(BUILD_DIR)/hls/$(CONF)/vta_compute/solution0/impl/ip/xilinx_com_hls_compute_1_0.zip
 
 # Bitstream file path
 BIT_PATH := $(BUILD_DIR)/vivado/$(CONF)/export/$(CONF).bit
 
-.PHONY: all ip bit bsp clean clean_all
+.PHONY: all ip bit clean clean_all
 
 all: bit
 ip: $(IP_PATH)
@@ -102,40 +83,52 @@ bit: $(BIT_PATH)
 $(IP_PATH): $(SRC_DIR)/*
 	mkdir -p $(IP_BUILD_PATH)
 	cd $(IP_BUILD_PATH) && \
-		$(VIVADO_HLS) -f $(SCRIPT_DIR)/hls.tcl \
-		-tclargs $(VTA_TARGET) \
-		$(SRC_DIR) $(SIM_DIR) $(TEST_DIR) $(INCLUDE_DIR) \
-		$(MODE) $(DEBUG) $(VTA_ALU_EN) $(VTA_MUL_EN) \
-		$(VTA_TARGET_PER) $(VTA_GEMM_II) $(VTA_TALU_II) \
-		$(VTA_INP_WIDTH) $(VTA_WGT_WIDTH) $(VTA_ACC_WIDTH) $(VTA_OUT_WIDTH) \
-		$(VTA_BATCH) $(VTA_IN_BLOCK) $(VTA_OUT_BLOCK) $(VTA_BUS_WIDTH) \
-		$(VTA_UOP_BUFF_SIZE) $(VTA_INP_BUFF_SIZE) $(VTA_WGT_BUFF_SIZE) \
-		$(VTA_ACC_BUFF_SIZE) $(VTA_OUT_BUFF_SIZE)
-ifeq ($(SLURM), True)
-	mkdir -p $(BUILD_DIR)/hls
-	mv $(IP_BUILD_PATH) $(BUILD_DIR)/hls/.
-endif
+		$(VIVADO_HLS) \
+		-f $(SCRIPT_DIR)/hls.tcl \
+		-tclargs \
+			$(VTA_TARGET) \
+			$(SRC_DIR) \
+			$(SIM_DIR) \
+			$(TEST_DIR) \
+			$(INCLUDE_DIR) \
+			$(VTA_TARGET_PER) \
+			$(VTA_INP_WIDTH) \
+			$(VTA_WGT_WIDTH) \
+			$(VTA_ACC_WIDTH) \
+			$(VTA_OUT_WIDTH) \
+			$(VTA_BATCH) \
+			$(VTA_IN_BLOCK) \
+			$(VTA_OUT_BLOCK) \
+			$(VTA_BUS_WIDTH) \
+			$(VTA_UOP_BUFF_SIZE) \
+			$(VTA_INP_BUFF_SIZE) \
+			$(VTA_WGT_BUFF_SIZE) \
+			$(VTA_ACC_BUFF_SIZE) \
+			$(VTA_OUT_BUFF_SIZE)
 
 $(BIT_PATH): $(IP_PATH)
 	mkdir -p $(HW_BUILD_PATH)
 	cd $(HW_BUILD_PATH) && \
-		$(VIVADO) -mode tcl -source $(SCRIPT_DIR)/vivado.tcl \
-		-tclargs $(VTA_TARGET) $(BUILD_DIR)/hls/$(CONF) $(VTA_HW_COMP_THREADS) \
-		$(VTA_CLOCK_FREQ) $(VTA_GEMM_II) \
-		$(VTA_INP_WIDTH) $(VTA_WGT_WIDTH) $(VTA_OUT_WIDTH) \
-		$(VTA_BATCH) $(VTA_IN_BLOCK) $(VTA_OUT_BLOCK) \
-		$(VTA_INP_BUFF_SIZE) $(VTA_WGT_BUFF_SIZE) $(VTA_OUT_BUFF_SIZE)
-ifeq ($(SLURM), True)
-	mkdir -p $(BUILD_DIR)/vivado
-	mv $(HW_BUILD_PATH) $(BUILD_DIR)/vivado/.
-endif
-
-bsp: $(BIT_PATH)
-	cd $(HW_BUILD_PATH) && $(HSI) -mode tcl -source $(SCRIPT_DIR)/hsi.tcl -nojournal -nolog
-	cd $(HW_BUILD_PATH)/bsp && make
+		$(VIVADO) \
+		-mode tcl \
+		-source $(SCRIPT_DIR)/vivado.tcl \
+		-tclargs \
+			$(VTA_TARGET) \
+			$(BUILD_DIR)/hls/$(CONF) \
+			$(VTA_HW_COMP_THREADS) \
+			$(VTA_CLOCK_FREQ) \
+			$(VTA_INP_WIDTH) \
+			$(VTA_WGT_WIDTH) \
+			$(VTA_OUT_WIDTH) \
+			$(VTA_BATCH) \
+			$(VTA_IN_BLOCK) \
+			$(VTA_OUT_BLOCK) \
+			$(VTA_INP_BUFF_SIZE) \
+			$(VTA_WGT_BUFF_SIZE) \
+			$(VTA_OUT_BUFF_SIZE)
 
 clean:
-	rm -rf *.out *.log *.sb figures
+	rm -rf *.out *.log
 
 cleanall: clean
 	rm -rf $(BUILD_DIR)