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Fix hanging bench_sigverify_stage_with_same_tx (#4141)
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apfitzge authored Dec 16, 2024
1 parent 3890ce5 commit e84db7f
Showing 1 changed file with 4 additions and 2 deletions.
6 changes: 4 additions & 2 deletions core/benches/sigverify_stage.rs
Original file line number Diff line number Diff line change
Expand Up @@ -175,18 +175,20 @@ fn bench_sigverify_stage(bencher: &mut Bencher, use_same_tx: bool) {
packet_s.send(batch).unwrap();
}
let mut received = 0;
trace!("sent: {}", sent_len);
let expected = if use_same_tx { 1 } else { sent_len };
trace!("sent: {}, expected: {}", sent_len, expected);
loop {
if let Ok(verifieds) = verified_r.recv_timeout(Duration::from_millis(10)) {
received += verifieds.iter().map(|batch| batch.len()).sum::<usize>();
test::black_box(verifieds);
if received >= sent_len {
if received >= expected {
break;
}
}
}
trace!("received: {}", received);
});
// This will wait for all packets to make it through sigverify.
stage.join().unwrap();
}

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