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Merge pull request rust-lang#311 from GuillaumeGomez/regen
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Regenerate intrinsics
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@antoyo
antoyo authored Aug 17, 2023
2 parents 4ad266a + d929cf8 commit 186320a
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Showing 2 changed files with 110 additions and 12 deletions.
114 changes: 106 additions & 8 deletions src/intrinsic/archs.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2254,6 +2254,42 @@ match name {
"llvm.hexagon.prefetch" => "__builtin_HEXAGON_prefetch",
"llvm.hexagon.vmemcpy" => "__builtin_hexagon_vmemcpy",
"llvm.hexagon.vmemset" => "__builtin_hexagon_vmemset",
// loongarch
"llvm.loongarch.asrtgt.d" => "__builtin_loongarch_asrtgt_d",
"llvm.loongarch.asrtle.d" => "__builtin_loongarch_asrtle_d",
"llvm.loongarch.break" => "__builtin_loongarch_break",
"llvm.loongarch.cacop.d" => "__builtin_loongarch_cacop_d",
"llvm.loongarch.cacop.w" => "__builtin_loongarch_cacop_w",
"llvm.loongarch.cpucfg" => "__builtin_loongarch_cpucfg",
"llvm.loongarch.crc.w.b.w" => "__builtin_loongarch_crc_w_b_w",
"llvm.loongarch.crc.w.d.w" => "__builtin_loongarch_crc_w_d_w",
"llvm.loongarch.crc.w.h.w" => "__builtin_loongarch_crc_w_h_w",
"llvm.loongarch.crc.w.w.w" => "__builtin_loongarch_crc_w_w_w",
"llvm.loongarch.crcc.w.b.w" => "__builtin_loongarch_crcc_w_b_w",
"llvm.loongarch.crcc.w.d.w" => "__builtin_loongarch_crcc_w_d_w",
"llvm.loongarch.crcc.w.h.w" => "__builtin_loongarch_crcc_w_h_w",
"llvm.loongarch.crcc.w.w.w" => "__builtin_loongarch_crcc_w_w_w",
"llvm.loongarch.csrrd.d" => "__builtin_loongarch_csrrd_d",
"llvm.loongarch.csrrd.w" => "__builtin_loongarch_csrrd_w",
"llvm.loongarch.csrwr.d" => "__builtin_loongarch_csrwr_d",
"llvm.loongarch.csrwr.w" => "__builtin_loongarch_csrwr_w",
"llvm.loongarch.csrxchg.d" => "__builtin_loongarch_csrxchg_d",
"llvm.loongarch.csrxchg.w" => "__builtin_loongarch_csrxchg_w",
"llvm.loongarch.dbar" => "__builtin_loongarch_dbar",
"llvm.loongarch.ibar" => "__builtin_loongarch_ibar",
"llvm.loongarch.iocsrrd.b" => "__builtin_loongarch_iocsrrd_b",
"llvm.loongarch.iocsrrd.d" => "__builtin_loongarch_iocsrrd_d",
"llvm.loongarch.iocsrrd.h" => "__builtin_loongarch_iocsrrd_h",
"llvm.loongarch.iocsrrd.w" => "__builtin_loongarch_iocsrrd_w",
"llvm.loongarch.iocsrwr.b" => "__builtin_loongarch_iocsrwr_b",
"llvm.loongarch.iocsrwr.d" => "__builtin_loongarch_iocsrwr_d",
"llvm.loongarch.iocsrwr.h" => "__builtin_loongarch_iocsrwr_h",
"llvm.loongarch.iocsrwr.w" => "__builtin_loongarch_iocsrwr_w",
"llvm.loongarch.lddir.d" => "__builtin_loongarch_lddir_d",
"llvm.loongarch.ldpte.d" => "__builtin_loongarch_ldpte_d",
"llvm.loongarch.movfcsr2gr" => "__builtin_loongarch_movfcsr2gr",
"llvm.loongarch.movgr2fcsr" => "__builtin_loongarch_movgr2fcsr",
"llvm.loongarch.syscall" => "__builtin_loongarch_syscall",
// mips
"llvm.mips.absq.s.ph" => "__builtin_mips_absq_s_ph",
"llvm.mips.absq.s.qb" => "__builtin_mips_absq_s_qb",
Expand Down Expand Up @@ -2954,6 +2990,8 @@ match name {
"llvm.nvvm.barrier0.and" => "__nvvm_bar0_and",
"llvm.nvvm.barrier0.or" => "__nvvm_bar0_or",
"llvm.nvvm.barrier0.popc" => "__nvvm_bar0_popc",
"llvm.nvvm.bf2h.rn" => "__nvvm_bf2h_rn",
"llvm.nvvm.bf2h.rn.ftz" => "__nvvm_bf2h_rn_ftz",
"llvm.nvvm.bitcast.d2ll" => "__nvvm_bitcast_d2ll",
"llvm.nvvm.bitcast.f2i" => "__nvvm_bitcast_f2i",
"llvm.nvvm.bitcast.i2f" => "__nvvm_bitcast_i2f",
Expand Down Expand Up @@ -3016,8 +3054,6 @@ match name {
"llvm.nvvm.div.rz.ftz.f" => "__nvvm_div_rz_ftz_f",
"llvm.nvvm.ex2.approx.d" => "__nvvm_ex2_approx_d",
"llvm.nvvm.ex2.approx.f" => "__nvvm_ex2_approx_f",
"llvm.nvvm.ex2.approx.f16" => "__nvvm_ex2_approx_f16",
"llvm.nvvm.ex2.approx.f16x2" => "__nvvm_ex2_approx_f16x2",
"llvm.nvvm.ex2.approx.ftz.f" => "__nvvm_ex2_approx_ftz_f",
"llvm.nvvm.f2bf16.rn" => "__nvvm_f2bf16_rn",
"llvm.nvvm.f2bf16.rn.relu" => "__nvvm_f2bf16_rn_relu",
Expand Down Expand Up @@ -3079,11 +3115,17 @@ match name {
"llvm.nvvm.fma.rn.bf16x2" => "__nvvm_fma_rn_bf16x2",
"llvm.nvvm.fma.rn.d" => "__nvvm_fma_rn_d",
"llvm.nvvm.fma.rn.f" => "__nvvm_fma_rn_f",
"llvm.nvvm.fma.rn.f16" => "__nvvm_fma_rn_f16",
"llvm.nvvm.fma.rn.f16x2" => "__nvvm_fma_rn_f16x2",
"llvm.nvvm.fma.rn.ftz.bf16" => "__nvvm_fma_rn_ftz_bf16",
"llvm.nvvm.fma.rn.ftz.bf16x2" => "__nvvm_fma_rn_ftz_bf16x2",
"llvm.nvvm.fma.rn.ftz.f" => "__nvvm_fma_rn_ftz_f",
"llvm.nvvm.fma.rn.ftz.relu.bf16" => "__nvvm_fma_rn_ftz_relu_bf16",
"llvm.nvvm.fma.rn.ftz.relu.bf16x2" => "__nvvm_fma_rn_ftz_relu_bf16x2",
"llvm.nvvm.fma.rn.ftz.sat.bf16" => "__nvvm_fma_rn_ftz_sat_bf16",
"llvm.nvvm.fma.rn.ftz.sat.bf16x2" => "__nvvm_fma_rn_ftz_sat_bf16x2",
"llvm.nvvm.fma.rn.relu.bf16" => "__nvvm_fma_rn_relu_bf16",
"llvm.nvvm.fma.rn.relu.bf16x2" => "__nvvm_fma_rn_relu_bf16x2",
"llvm.nvvm.fma.rn.sat.bf16" => "__nvvm_fma_rn_sat_bf16",
"llvm.nvvm.fma.rn.sat.bf16x2" => "__nvvm_fma_rn_sat_bf16x2",
"llvm.nvvm.fma.rp.d" => "__nvvm_fma_rp_d",
"llvm.nvvm.fma.rp.f" => "__nvvm_fma_rp_f",
"llvm.nvvm.fma.rp.ftz.f" => "__nvvm_fma_rp_ftz_f",
Expand All @@ -3094,11 +3136,17 @@ match name {
"llvm.nvvm.fmax.bf16x2" => "__nvvm_fmax_bf16x2",
"llvm.nvvm.fmax.d" => "__nvvm_fmax_d",
"llvm.nvvm.fmax.f" => "__nvvm_fmax_f",
"llvm.nvvm.fmax.f16" => "__nvvm_fmax_f16",
"llvm.nvvm.fmax.f16x2" => "__nvvm_fmax_f16x2",
"llvm.nvvm.fmax.ftz.bf16" => "__nvvm_fmax_ftz_bf16",
"llvm.nvvm.fmax.ftz.bf16x2" => "__nvvm_fmax_ftz_bf16x2",
"llvm.nvvm.fmax.ftz.f" => "__nvvm_fmax_ftz_f",
"llvm.nvvm.fmax.ftz.nan.bf16" => "__nvvm_fmax_ftz_nan_bf16",
"llvm.nvvm.fmax.ftz.nan.bf16x2" => "__nvvm_fmax_ftz_nan_bf16x2",
"llvm.nvvm.fmax.ftz.nan.f" => "__nvvm_fmax_ftz_nan_f",
"llvm.nvvm.fmax.ftz.nan.xorsign.abs.bf16" => "__nvvm_fmax_ftz_nan_xorsign_abs_bf16",
"llvm.nvvm.fmax.ftz.nan.xorsign.abs.bf16x2" => "__nvvm_fmax_ftz_nan_xorsign_abs_bf16x2",
"llvm.nvvm.fmax.ftz.nan.xorsign.abs.f" => "__nvvm_fmax_ftz_nan_xorsign_abs_f",
"llvm.nvvm.fmax.ftz.xorsign.abs.bf16" => "__nvvm_fmax_ftz_xorsign_abs_bf16",
"llvm.nvvm.fmax.ftz.xorsign.abs.bf16x2" => "__nvvm_fmax_ftz_xorsign_abs_bf16x2",
"llvm.nvvm.fmax.ftz.xorsign.abs.f" => "__nvvm_fmax_ftz_xorsign_abs_f",
"llvm.nvvm.fmax.nan.bf16" => "__nvvm_fmax_nan_bf16",
"llvm.nvvm.fmax.nan.bf16x2" => "__nvvm_fmax_nan_bf16x2",
Expand All @@ -3113,11 +3161,17 @@ match name {
"llvm.nvvm.fmin.bf16x2" => "__nvvm_fmin_bf16x2",
"llvm.nvvm.fmin.d" => "__nvvm_fmin_d",
"llvm.nvvm.fmin.f" => "__nvvm_fmin_f",
"llvm.nvvm.fmin.f16" => "__nvvm_fmin_f16",
"llvm.nvvm.fmin.f16x2" => "__nvvm_fmin_f16x2",
"llvm.nvvm.fmin.ftz.bf16" => "__nvvm_fmin_ftz_bf16",
"llvm.nvvm.fmin.ftz.bf16x2" => "__nvvm_fmin_ftz_bf16x2",
"llvm.nvvm.fmin.ftz.f" => "__nvvm_fmin_ftz_f",
"llvm.nvvm.fmin.ftz.nan.bf16" => "__nvvm_fmin_ftz_nan_bf16",
"llvm.nvvm.fmin.ftz.nan.bf16x2" => "__nvvm_fmin_ftz_nan_bf16x2",
"llvm.nvvm.fmin.ftz.nan.f" => "__nvvm_fmin_ftz_nan_f",
"llvm.nvvm.fmin.ftz.nan.xorsign.abs.bf16" => "__nvvm_fmin_ftz_nan_xorsign_abs_bf16",
"llvm.nvvm.fmin.ftz.nan.xorsign.abs.bf16x2" => "__nvvm_fmin_ftz_nan_xorsign_abs_bf16x2",
"llvm.nvvm.fmin.ftz.nan.xorsign.abs.f" => "__nvvm_fmin_ftz_nan_xorsign_abs_f",
"llvm.nvvm.fmin.ftz.xorsign.abs.bf16" => "__nvvm_fmin_ftz_xorsign_abs_bf16",
"llvm.nvvm.fmin.ftz.xorsign.abs.bf16x2" => "__nvvm_fmin_ftz_xorsign_abs_bf16x2",
"llvm.nvvm.fmin.ftz.xorsign.abs.f" => "__nvvm_fmin_ftz_xorsign_abs_f",
"llvm.nvvm.fmin.nan.bf16" => "__nvvm_fmin_nan_bf16",
"llvm.nvvm.fmin.nan.bf16x2" => "__nvvm_fmin_nan_bf16x2",
Expand Down Expand Up @@ -4213,6 +4267,28 @@ match name {
"llvm.r600.read.tgid.x" => "__builtin_r600_read_tgid_x",
"llvm.r600.read.tgid.y" => "__builtin_r600_read_tgid_y",
"llvm.r600.read.tgid.z" => "__builtin_r600_read_tgid_z",
// riscv
"llvm.riscv.aes32dsi" => "__builtin_riscv_aes32dsi",
"llvm.riscv.aes32dsmi" => "__builtin_riscv_aes32dsmi",
"llvm.riscv.aes32esi" => "__builtin_riscv_aes32esi",
"llvm.riscv.aes32esmi" => "__builtin_riscv_aes32esmi",
"llvm.riscv.aes64ds" => "__builtin_riscv_aes64ds",
"llvm.riscv.aes64dsm" => "__builtin_riscv_aes64dsm",
"llvm.riscv.aes64es" => "__builtin_riscv_aes64es",
"llvm.riscv.aes64esm" => "__builtin_riscv_aes64esm",
"llvm.riscv.aes64im" => "__builtin_riscv_aes64im",
"llvm.riscv.aes64ks1i" => "__builtin_riscv_aes64ks1i",
"llvm.riscv.aes64ks2" => "__builtin_riscv_aes64ks2",
"llvm.riscv.sha512sig0" => "__builtin_riscv_sha512sig0",
"llvm.riscv.sha512sig0h" => "__builtin_riscv_sha512sig0h",
"llvm.riscv.sha512sig0l" => "__builtin_riscv_sha512sig0l",
"llvm.riscv.sha512sig1" => "__builtin_riscv_sha512sig1",
"llvm.riscv.sha512sig1h" => "__builtin_riscv_sha512sig1h",
"llvm.riscv.sha512sig1l" => "__builtin_riscv_sha512sig1l",
"llvm.riscv.sha512sum0" => "__builtin_riscv_sha512sum0",
"llvm.riscv.sha512sum0r" => "__builtin_riscv_sha512sum0r",
"llvm.riscv.sha512sum1" => "__builtin_riscv_sha512sum1",
"llvm.riscv.sha512sum1r" => "__builtin_riscv_sha512sum1r",
// s390
"llvm.s390.efpc" => "__builtin_s390_efpc",
"llvm.s390.etnd" => "__builtin_tx_nesting_depth",
Expand Down Expand Up @@ -5912,6 +5988,18 @@ match name {
"llvm.x86.avx2.vpdpbuud.256" => "__builtin_ia32_vpdpbuud256",
"llvm.x86.avx2.vpdpbuuds.128" => "__builtin_ia32_vpdpbuuds128",
"llvm.x86.avx2.vpdpbuuds.256" => "__builtin_ia32_vpdpbuuds256",
"llvm.x86.avx2.vpdpwsud.128" => "__builtin_ia32_vpdpwsud128",
"llvm.x86.avx2.vpdpwsud.256" => "__builtin_ia32_vpdpwsud256",
"llvm.x86.avx2.vpdpwsuds.128" => "__builtin_ia32_vpdpwsuds128",
"llvm.x86.avx2.vpdpwsuds.256" => "__builtin_ia32_vpdpwsuds256",
"llvm.x86.avx2.vpdpwusd.128" => "__builtin_ia32_vpdpwusd128",
"llvm.x86.avx2.vpdpwusd.256" => "__builtin_ia32_vpdpwusd256",
"llvm.x86.avx2.vpdpwusds.128" => "__builtin_ia32_vpdpwusds128",
"llvm.x86.avx2.vpdpwusds.256" => "__builtin_ia32_vpdpwusds256",
"llvm.x86.avx2.vpdpwuud.128" => "__builtin_ia32_vpdpwuud128",
"llvm.x86.avx2.vpdpwuud.256" => "__builtin_ia32_vpdpwuud256",
"llvm.x86.avx2.vpdpwuuds.128" => "__builtin_ia32_vpdpwuuds128",
"llvm.x86.avx2.vpdpwuuds.256" => "__builtin_ia32_vpdpwuuds256",
"llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256",
"llvm.x86.avx512.add.pd.512" => "__builtin_ia32_addpd512",
"llvm.x86.avx512.add.ps.512" => "__builtin_ia32_addps512",
Expand Down Expand Up @@ -7909,6 +7997,16 @@ match name {
"llvm.x86.vgf2p8mulb.128" => "__builtin_ia32_vgf2p8mulb_v16qi",
"llvm.x86.vgf2p8mulb.256" => "__builtin_ia32_vgf2p8mulb_v32qi",
"llvm.x86.vgf2p8mulb.512" => "__builtin_ia32_vgf2p8mulb_v64qi",
"llvm.x86.vsha512msg1" => "__builtin_ia32_vsha512msg1",
"llvm.x86.vsha512msg2" => "__builtin_ia32_vsha512msg2",
"llvm.x86.vsha512rnds2" => "__builtin_ia32_vsha512rnds2",
"llvm.x86.vsm3msg1" => "__builtin_ia32_vsm3msg1",
"llvm.x86.vsm3msg2" => "__builtin_ia32_vsm3msg2",
"llvm.x86.vsm3rnds2" => "__builtin_ia32_vsm3rnds2",
"llvm.x86.vsm4key4128" => "__builtin_ia32_vsm4key4128",
"llvm.x86.vsm4key4256" => "__builtin_ia32_vsm4key4256",
"llvm.x86.vsm4rnds4128" => "__builtin_ia32_vsm4rnds4128",
"llvm.x86.vsm4rnds4256" => "__builtin_ia32_vsm4rnds4256",
"llvm.x86.wbinvd" => "__builtin_ia32_wbinvd",
"llvm.x86.wbnoinvd" => "__builtin_ia32_wbnoinvd",
"llvm.x86.wrfsbase.32" => "__builtin_ia32_wrfsbase32",
Expand Down
8 changes: 4 additions & 4 deletions tools/generate_intrinsics.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -46,10 +46,10 @@ def convert_to_string(content):


def extract_instrinsics_from_llvm(llvm_path, intrinsics):
p = subprocess.Popen(
["llvm-tblgen", "llvm/IR/Intrinsics.td"],
cwd=os.path.join(llvm_path, "llvm/include"),
stdout=subprocess.PIPE)
command = ["llvm-tblgen", "llvm/IR/Intrinsics.td"]
cwd = os.path.join(llvm_path, "llvm/include")
print("=> Running command `{}` from `{}`".format(command, cwd))
p = subprocess.Popen(command, cwd=cwd, stdout=subprocess.PIPE)
output, err = p.communicate()
lines = convert_to_string(output).splitlines()
pos = 0
Expand Down

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