Merge pull request #21 from hermanschmit/fixMultiplierBitwidth

Fixed odd bitwidth bug.
antonblanchard · May 8, 2023 · 292ac2a · 292ac2a
2 parents fa26e72 + 7a151e8
commit 292ac2a
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Showing 3 changed files with 64 additions and 9 deletions.
diff --git a/tests/test_multiplier.py b/tests/test_multiplier.py
@@ -15,7 +15,7 @@ class TestMultiplier(Multiplier, BoothRadix4, Dadda, NoneProcess):
     pass
 
 
-class TestCaseRandom(unittest.TestCase):
+class TestCaseRandom32(unittest.TestCase):
     def setUp(self):
         self.bits = 32
         self.dut = TestMultiplier(adder=TestAdder, bits=self.bits)
@@ -36,7 +36,32 @@ def bench():
 
         sim = Simulator(self.dut)
         sim.add_process(bench)
-        with sim.write_vcd("multiplier_random.vcd"):
+        with sim.write_vcd("multiplier_random32.vcd"):
+            sim.run()
+
+
+class TestCaseRandom23(unittest.TestCase):
+    def setUp(self):
+        self.bits = 23
+        self.dut = TestMultiplier(adder=TestAdder, bits=self.bits)
+
+    def do_one_comb(self, a, b):
+        yield self.dut.a.eq(a)
+        yield self.dut.b.eq(b)
+        yield Settle()
+        res = (yield self.dut.o)
+        self.assertEqual(res, a * b)
+
+    def test_random(self):
+        def bench():
+            for i in range(100):
+                rand_a = random.getrandbits(self.bits)
+                rand_b = random.getrandbits(self.bits)
+                yield from self.do_one_comb(rand_a, rand_b)
+
+        sim = Simulator(self.dut)
+        sim.add_process(bench)
+        with sim.write_vcd("multiplier_random23.vcd"):
             sim.run()
 
 

diff --git a/tests/test_multiplier_exhaustive.py b/tests/test_multiplier_exhaustive.py
@@ -15,7 +15,7 @@ class TestMultiplier(Multiplier, BoothRadix4, Dadda, NoneProcess):
     pass
 
 
-class TestCaseExhaustive(unittest.TestCase):
+class TestCaseExhaustive8(unittest.TestCase):
     def setUp(self):
         self.bits = 8
         self.dut = TestMultiplier(adder=TestAdder, bits=self.bits)
@@ -35,7 +35,31 @@ def bench():
 
         sim = Simulator(self.dut)
         sim.add_process(bench)
-        with sim.write_vcd("multiplier_exhaustive.vcd"):
+        with sim.write_vcd("multiplier_exhaustive8.vcd"):
+            sim.run()
+
+
+class TestCaseExhaustive7(unittest.TestCase):
+    def setUp(self):
+        self.bits = 7
+        self.dut = TestMultiplier(adder=TestAdder, bits=self.bits)
+
+    def do_one_comb(self, a, b):
+        yield self.dut.a.eq(a)
+        yield self.dut.b.eq(b)
+        yield Settle()
+        res = (yield self.dut.o)
+        self.assertEqual(res, a * b)
+
+    def test_exhaustive(self):
+        def bench():
+            for a in range(int(math.pow(self.bits, 2))):
+                for b in range(int(math.pow(self.bits, 2))):
+                    yield from self.do_one_comb(a, b)
+
+        sim = Simulator(self.dut)
+        sim.add_process(bench)
+        with sim.write_vcd("multiplier_exhaustive7.vcd"):
             sim.run()
 
 

diff --git a/vlsiffra/multiplier.py b/vlsiffra/multiplier.py
@@ -170,12 +170,18 @@ def _gen_partial_products(self):
         multiplicand = Signal(self._bits + 2)
 
         # Add a zero in the LSB of the multiplier and multiplicand
-        self.m.d.comb += [
-            multiplier.eq(Cat(Const(0), self.a_registered, Const(0), Const(0))),
-            multiplicand.eq(Cat(Const(0), self.b_registered, Const(0))),
-        ]
+        if self._bits % 2 == 0:
+            self.m.d.comb += [
+                multiplier.eq(Cat(Const(0), self.a_registered, Const(0), Const(0))),
+                multiplicand.eq(Cat(Const(0), self.b_registered, Const(0))),
+            ]
+        else:
+            self.m.d.comb += [
+                multiplier.eq(Cat(Const(0), self.a_registered, Const(0))),
+                multiplicand.eq(Cat(Const(0), self.b_registered, Const(0))),
+            ]
 
-        last_b = self._bits
+        last_b = self._bits - self._bits % 2
         last_m = self._bits
 
         # Step through the multiplier 2 bits at a time