Add Microwatt

This adds the Microwatt 64 bit OpenPOWER core with the FPU enabled
and 4kB of DFFRAM.

README.md

@@ -2,11 +2,12 @@
 
 [![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![UPRJ_CI](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [![Caravel Build](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml)
 
-| :exclamation: Important Note            |
-|-----------------------------------------|
+Microwatt on Caravel
+====================
 
-## Please fill in your project documentation in this README.md file 
+The Microwatt 64 bit OpenPOWER core integrated into the Caravel SKY130 shuttles.
 
-Refer to [README](docs/source/quickstart.rst) for a quick start of how to use caravel_user_project
+Tests
+=====
 
-Refer to [README](docs/source/index.rst) for this sample project documentation. 
+- Check out verilog/dv/caravel/microwatt/README.md

openlane/Microwatt_FP_DFFRFile/base.sdc

@@ -0,0 +1,21 @@
+create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
+set_propagated_clock [get_clocks $::env(CLOCK_PORT)]
+
+# We don't constrain I/Os in the macros, and instead adjust constraints in the
+# final integration to avoid hold violations.
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
+puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
+set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks $::env(CLOCK_PORT)]
+
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks $::env(CLOCK_PORT)]
+
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]

openlane/Microwatt_FP_DFFRFile/config.tcl

@@ -0,0 +1,66 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) Microwatt_FP_DFFRFile
+
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/Microwatt_FP_DFFRFile.v"
+
+set ::env(CLOCK_PORT) "CLK"
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+set ::env(BASE_SDC_FILE) $script_dir/base.sdc
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 1150 1150"
+
+# Settings for macros
+set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(RT_MAX_LAYER) "met4"
+
+# Handle PDN
+set ::env(VDD_NETS) [list {VPWR} ]
+set ::env(GND_NETS) [list {VGND} ]
+
+# Make PDN match top level
+set ::env(FP_PDN_VWIDTH) 3.1
+set ::env(FP_PDN_HWIDTH) 3.1
+set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_VWIDTH)]
+set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_HWIDTH)]
+
+# PDN Pitch
+set ::env(FP_PDN_VPITCH) 180
+set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH)
+
+# PDN Offset
+set ::env(FP_PDN_VOFFSET) 5
+set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET)
+
+# Tuning
+set ::env(PL_TARGET_DENSITY) 0.33
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+if {[catch {exec nproc} result] == 0} {
+	set ::env(ROUTING_CORES) $result
+} else {
+	set ::env(ROUTING_CORES) 4
+}
+
+#set ::env(IO_PCT) 0.5
+
+#set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) "0.5"
+set ::env(ECO_ENABLE) 1
+#set ::env(ECO_SKIP_PIN) 0
+
+set ::env(DIODE_INSERTION_STRATEGY) 0
+
+#set ::env(PL_ROUTABILITY_DRIVEN) 1
+#set ::env(PL_TIME_DRIVEN) 1
+
+set ::env(SYNTH_STRATEGY) {DELAY 4}
+
+# CTS tuning
+set ::env(CTS_DISABLE_POST_PROCESSING) 1
+
+set ::env(RUN_KLAYOUT) 0

openlane/Microwatt_FP_DFFRFile/pin_order.cfg

@@ -0,0 +1,15 @@
+#N
+CLK
+WE
+R1\[.*
+R2\[.*
+R3\[.*
+RW\[.*
+
+#W
+D1\[.*
+D2\[.*
+
+#S
+D3\[.*
+DW\[.*

openlane/multiply_add_64x64/base.sdc

@@ -0,0 +1,21 @@
+create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
+set_propagated_clock [get_clocks $::env(CLOCK_PORT)]
+
+# We don't constrain I/Os in the macros, and instead adjust constraints in the
+# final integration to avoid hold violations.
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
+puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
+set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks $::env(CLOCK_PORT)]
+
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks $::env(CLOCK_PORT)]
+
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]

openlane/multiply_add_64x64/config.tcl

@@ -0,0 +1,80 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) multiply_add_64x64
+
+set ::env(VERILOG_FILES) "\
+	$script_dir/src/multiply_add_64x64.v"
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+set ::env(BASE_SDC_FILE) $script_dir/base.sdc
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 550 550"
+
+# Settings for macros
+set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(RT_MAX_LAYER) "met4"
+
+# Handle PDN
+set ::env(VDD_NETS) [list {VPWR} ]
+set ::env(GND_NETS) [list {VGND} ]
+
+# Make PDN match top level
+set ::env(FP_PDN_VWIDTH) 3.1
+set ::env(FP_PDN_HWIDTH) 3.1
+set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_VWIDTH)]
+set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_HWIDTH)]
+
+# PDN Pitch
+set ::env(FP_PDN_VPITCH) 180
+set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH)
+
+# PDN Offset
+set ::env(FP_PDN_VOFFSET) 5
+set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET)
+
+# Tuning
+set ::env(PL_TARGET_DENSITY) 0.36
+
+# Because the macro uses standard cells
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+if {[catch {exec nproc} result] == 0} {
+	set ::env(ROUTING_CORES) $result
+} else {
+	set ::env(ROUTING_CORES) 4
+}
+
+#set ::env(IO_PCT) 0.5
+
+#set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) "0.4"
+set ::env(ECO_ENABLE) 1
+#set ::env(ECO_SKIP_PIN) 0
+
+# Still seeing SEGVs in OpenROAD unless we disable diode insertion
+set ::env(DIODE_INSERTION_STRATEGY) 0
+
+set ::env(PL_ROUTABILITY_DRIVEN) 1
+set ::env(PL_TIME_DRIVEN) 1
+
+set ::env(SYNTH_STRATEGY) {DELAY 4}
+
+# CTS tuning
+set ::env(CTS_DISABLE_POST_PROCESSING) 1
+
+set ::env(RUN_KLAYOUT) 0
+
+# Hacking
+
+# ext2spice is failing when using the LEF
+##set ::env(MAGIC_EXT_USE_GDS) 1
+# This doesn't work with a gds.spice file for some reason
+##set ::env(RUN_CVC) 0
+
+# Why was this disabled upstream recently?
+##set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1

openlane/multiply_add_64x64/pin_order.cfg

@@ -0,0 +1,11 @@
+#N
+o\[.*
+rst
+clk
+
+#E
+a\[.*
+b\[.*
+
+#S
+c\[.*