DSLX DMA: Implementation

Signed-off-by: Michal Czyz <[email protected]>

.github/actions/build/action.yml

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+name: build
+description: 'Build XLS'
+
+runs:
+  using: "composite"
+  steps:
+    - name: Cache
+      uses: ./.github/actions/cache
+
+    - name: Install dependencies via apt
+      shell: bash
+      run: sudo apt-get install python3-distutils python3-dev python-is-python3 libtinfo5  build-essential liblapack-dev libblas-dev gfortran
+
+    - name: Install bazelisk
+      shell: bash
+      run: |
+        curl -LO "https://github.com/bazelbuild/bazelisk/releases/download/v1.19.0/bazelisk-linux-amd64"
+        mkdir -p "${GITHUB_WORKSPACE}/bin/"
+        mv bazelisk-linux-amd64 "${GITHUB_WORKSPACE}/bin/bazel"
+        chmod +x "${GITHUB_WORKSPACE}/bin/bazel"
+
+    - name: Bazel Build Tools (opt)
+      shell: bash
+      run: |
+        "${GITHUB_WORKSPACE}/bin/bazel" build --local_cpu_resources=HOST_CPUS-1 --local_ram_resources=HOST_RAM*.9 -c opt --test_output=errors -- //xls/dslx:interpreter_main //xls/dslx/ir_convert:ir_converter_main //xls/tools:opt_main //xls/tools:codegen_main
+

.github/actions/cache/action.yml

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+name: cache
+description: 'Cache Bazel'
+
+runs:
+  using: "composite"
+  steps:
+    - name: Mount Bazel Cache
+      uses: actions/cache@v4
+      with:
+        path: "~/.cache/bazel"
+        # Create/use a cache called bazel-cache-22_04-<commit hash>
+        # and read the latest cache with prefix bazel-cache-22_04-
+        # if it doesn't already exist.
+        key: bazel-cache-22_04-${{ github.sha }}
+        restore-keys: bazel-cache-22_04-

.github/actions/free-disk/action.yml

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+name: free-disk
+description: 'Removes unused files from runner'
+
+# WARNING
+# This is not a 100% safe method of reclaiming space.
+# Your workflow may depend on removed files.
+
+runs:
+  using: "composite"
+  steps:
+    - name: Increase build space
+      shell: bash
+      run: |
+        echo "Before cleanup"
+        df -H
+        sudo rm -rf /usr/share/dotnet/*
+        sudo rm -rf /usr/local/lib/android/*
+        sudo rm -rf /usr/share/dotnet
+        sudo rm -rf /opt/ghc
+        sudo rm -rf "/usr/local/share/boost"
+        sudo rm -rf "$AGENT_TOOLSDIRECTORY"
+        echo "After cleanup"
+        df -H

.github/actions/implementation/action.yml

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+name: implementation
+description: 'DSLX to Openroad P&R'
+inputs:
+  xls_module:
+    description: 'Module in //xls/modules'
+    required: true
+    default: 'xls/modules/dma'
+  rule_ir:
+    description: 'Bazel rule to generate optimized IR'
+    required: true
+    default: 'csr_opt_ir_benchmark'
+  rule_verilog:
+    description: 'Bazel rule to generate verilog'
+    required: true
+    default: 'verilog_csr'
+  rule_synthesis:
+    description: 'Bazel rule to synthesize verilog'
+    required: true
+    default: 'csr_benchmark_synth'
+  rule_pnr:
+    description: 'Bazel rule to place and route'
+    required: true
+    default: 'csr_place_and_route'
+runs:
+  using: "composite"
+  steps:
+    - uses: ./.github/actions/cache
+
+    - name: Summary page
+      shell: bash
+      run: |
+        echo "Module ${{inputs.xls_module}}" >> $GITHUB_STEP_SUMMARY
+
+    - name: IR
+      shell: bash
+      run: |
+        bazel run --local_cpu_resources=HOST_CPUS-1 --local_ram_resources=HOST_RAM*.9 ${{inputs.xls_module}}:${{inputs.rule_ir}}
+
+    - name: Summary page
+      shell: bash
+      run: |
+        echo "Generate IR :white_check_mark:" >> $GITHUB_STEP_SUMMARY
+
+    - name: Verilog
+      shell: bash
+      run: |
+        bazel build --local_cpu_resources=HOST_CPUS-1 --local_ram_resources=HOST_RAM*.9 ${{inputs.xls_module}}:${{inputs.rule_verilog}}
+
+    - name: Summary page
+      shell: bash
+      run: |
+        echo "Verilog codegen :white_check_mark:" >> $GITHUB_STEP_SUMMARY
+
+    - name: Synthesis
+      shell: bash
+      run: |
+        bazel run --local_cpu_resources=HOST_CPUS-1 --local_ram_resources=HOST_RAM*.9 ${{inputs.xls_module}}:${{inputs.rule_synthesis}}
+
+    - name: Summary page
+      shell: bash
+      run: |
+        echo -n "Synthesis :white_check_mark:" >> $GITHUB_STEP_SUMMARY
+
+    - name: P&R
+      shell: bash
+      run: |
+        bazel build --local_cpu_resources=HOST_CPUS-1 --local_ram_resources=HOST_RAM*.9 ${{inputs.xls_module}}:${{inputs.rule_pnr}}
+
+    - name: Summary page
+      shell: bash
+      run: |
+        echo -n "Place & Route :white_check_mark:" >> $GITHUB_STEP_SUMMARY
+
+      # ${variable/character_to_replace/new_character}
+      # ${variable/ slash / underscore }
+    - name: Prepare artifact name
+      if: always()
+      shell: bash
+      run: |
+        name_input=${{inputs.xls_module}}/${{inputs.rule_ir}}
+        name_output="${name_input//\//_}"
+        echo "artifact_name=${name_output}" >> "$GITHUB_ENV"
+
+    - name: Artifacts
+      if: always()
+      uses: actions/upload-artifact@v4
+      with:
+        name: artifacts-impl-${{ env.artifact_name }}
+        path: |
+          ./bazel-bin/${{inputs.xls_module}}/*.log
+          ./bazel-bin/${{inputs.xls_module}}/*.textproto
+          ./bazel-bin/${{inputs.xls_module}}/*.ir
+          ./bazel-bin/${{inputs.xls_module}}/*.v
+          ./bazel-bin/${{inputs.xls_module}}/*.sv

.github/actions/test/action.yml

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+name: test
+description: 'DSLX Test'
+inputs:
+  xls_module:
+    description: 'Module in //xls/modules'
+    required: true
+    default: 'xls/modules/dma'
+  rule_test:
+    description: 'Bazel rule to test DSLX'
+    required: true
+    default: 'test_csr'
+
+runs:
+  using: "composite"
+  steps:
+    - uses: ./.github/actions/cache
+
+    - name: IR
+      shell: bash
+      env:
+        BAZEL_RESOURCES_OPT: "--local_cpu_resources=HOST_CPUS-1 --local_ram_resources=HOST_RAM*.9"
+        BAZEL_RUN_OPT: ""
+      run: |
+        bazel run ${BAZEL_RESOURCES_OPT} ${BAZEL_RUN_OPT} ${{inputs.xls_module}}/${{inputs.rule_test}}

.github/scripts/validate_json.py

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+# Copyright 2024 The XLS Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import json
+import os
+
+# Execution
+# In root dir: python .github/scripts/validate_json.py
+
+# This script uses bazel query to check if each target defined
+# in the xls-modules.json exists in the BUILD.
+
+json_file = open('.github/workflows/xls-modules.json')
+
+data = json.load(json_file)
+json_file.close()
+
+bazel_rules = []
+for module in data['module']:
+    for type in ["rule_ir", "rule_verilog", "rule_synthesis", "rule_pnr"]:
+        bazel_rule = "bazel query " + module['xls_module'] + ":" + module[type]
+        bazel_rules.append(bazel_rule)
+
+for bazel_rule in bazel_rules:
+    RC = os.system(bazel_rule)
+    assert RC == 0

.github/workflows/xls-modules.json

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+{
+  "module": [
+    {
+        "xls_module": "//xls/modules/dma",
+        "rule_ir": "csr_opt_ir_benchmark",
+        "rule_verilog": "verilog_csr",
+        "rule_synthesis": "csr_benchmark_synth",
+        "rule_pnr": "csr_place_and_route"
+    },
+    {
+      "xls_module": "//xls/modules/dma",
+      "rule_ir": "axi_csr_opt_ir_benchmark",
+      "rule_verilog": "verilog_axi_csr",
+      "rule_synthesis": "axi_csr_benchmark_synth",
+      "rule_pnr": "axi_csr_place_and_route"
+    },
+    {
+      "xls_module": "//xls/modules/dma",
+      "rule_ir": "address_generator_opt_ir_benchmark",
+      "rule_verilog": "verilog_address_generator",
+      "rule_synthesis": "address_generator_benchmark_synth",
+      "rule_pnr": "address_generator_place_and_route"
+    },
+    {
+      "xls_module": "//xls/modules/dma",
+      "rule_ir": "frontend_reader_opt_ir_benchmark",
+      "rule_verilog": "verilog_frontend_reader",
+      "rule_synthesis": "frontend_reader_benchmark_synth",
+      "rule_pnr": "frontend_reader_place_and_route"
+    },
+    {
+      "xls_module": "//xls/modules/dma",
+      "rule_ir": "frontend_writer_opt_ir_benchmark",
+      "rule_verilog": "verilog_frontend_writer",
+      "rule_synthesis": "frontend_writer_benchmark_synth",
+      "rule_pnr": "frontend_writer_place_and_route"
+    }
+  ]
+}