Skip to content

Commit

Permalink
[TEMP] modules/zstd/benchmarks: Disable benchmarks
Browse files Browse the repository at this point in the history
Not able to generate verilog code due to broken IR optimization
see google#1455

Internal-tag: [#52186]
Signed-off-by: Pawel Czarnecki <[email protected]>
  • Loading branch information
lpawelcz committed Jun 12, 2024
1 parent 1f4b0d1 commit 0030b1e
Showing 1 changed file with 622 additions and 621 deletions.
Loading

0 comments on commit 0030b1e

Please sign in to comment.