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Merge pull request #1 from antmicro/develop
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kgugala authored Apr 23, 2020
2 parents b94bb31 + 4fa99d2 commit 022a9df
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Showing 19 changed files with 34,405 additions and 8 deletions.
18 changes: 14 additions & 4 deletions .travis.yml
Original file line number Diff line number Diff line change
@@ -1,14 +1,20 @@
os: linux
dist: bionic
language: c++
env:
global:
- DEBIAN_FRONTEND: noninteractive
addons:
apt:
packages:
- wget
- locales

before_install:
- export DEBIAN_FRONTEND=noninteractive

install:
- sudo apt-get update && sudo apt-get install -y wget locales
- sudo locale-gen "en_US.UTF-8"
- export LANG="en_US.UTF-8"

install:
- wget https://repo.anaconda.com/miniconda/Miniconda3-latest-Linux-x86_64.sh -O miniconda.sh
- bash miniconda.sh -b -p $HOME/miniconda
- source "$HOME/miniconda/etc/profile.d/conda.sh"
Expand All @@ -30,3 +36,7 @@ script:
- export PATH=$TRAVIS_BUILD_DIR/install/bin:$PATH
- cd $TRAVIS_BUILD_DIR/counter_test
- make
- cd $TRAVIS_BUILD_DIR/picosoc_demo
- make
- cd $TRAVIS_BUILD_DIR/linux_litex_demo
- make
9 changes: 5 additions & 4 deletions counter_test/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,8 @@ VERILOG:=${current_dir}/counter_basys3.v
PARTNAME:= xc7a35tcpg236-1
DEVICE := xc7a50t_test
BITSTREAM_DEVICE := artix7
PCF=${current_dir}/basys3.pcf
PCF:=${current_dir}/basys3.pcf
SDC:=${current_dir}/basys3.sdc
BUILDDIR:=build

all: ${BUILDDIR}/${TOP}.bit
Expand All @@ -17,13 +18,13 @@ ${BUILDDIR}/${TOP}.eblif: | ${BUILDDIR}
cd ${BUILDDIR} && synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME}

${BUILDDIR}/${TOP}.net: ${BUILDDIR}/${TOP}.eblif
cd ${BUILDDIR} && pack -e ${TOP}.eblif -d ${DEVICE}
cd ${BUILDDIR} && pack -e ${TOP}.eblif -d ${DEVICE} -s ${SDC}

${BUILDDIR}/${TOP}.place: ${BUILDDIR}/${TOP}.net
cd ${BUILDDIR} && place -e ${TOP}.eblif -d ${DEVICE} -p ${PCF} -n ${TOP}.net -P ${PARTNAME}
cd ${BUILDDIR} && place -e ${TOP}.eblif -d ${DEVICE} -p ${PCF} -n ${TOP}.net -P ${PARTNAME} -s ${SDC} 2>&1 > /dev/null

${BUILDDIR}/${TOP}.route: ${BUILDDIR}/${TOP}.place
cd ${BUILDDIR} && route -e ${TOP}.eblif -d ${DEVICE}
cd ${BUILDDIR} && route -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null

${BUILDDIR}/${TOP}.fasm: ${BUILDDIR}/${TOP}.route
cd ${BUILDDIR} && write_fasm -e ${TOP}.eblif -d ${DEVICE}
Expand Down
1 change: 1 addition & 0 deletions counter_test/basys3.sdc
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
create_clock -period 10 bufg
42 changes: 42 additions & 0 deletions linux_litex_demo/Makefile
Original file line number Diff line number Diff line change
@@ -0,0 +1,42 @@
mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
current_dir := $(patsubst %/,%,$(dir $(mkfile_path)))
TOP := top
VERILOG := ${current_dir}/baselitex_arty.v \
${current_dir}/VexRiscv_Linux.v
MEM_INIT := ${current_dir}/mem.init \
${current_dir}/mem_1.init \
${current_dir}/mem_2.init
PARTNAME := xc7a35tcsg324-1
DEVICE := xc7a50t_test
BITSTREAM_DEVICE := artix7
PCF := ${current_dir}/arty.pcf
SDC := ${current_dir}/arty.sdc
BUILDDIR := build

all: ${BUILDDIR}/${TOP}.bit

${BUILDDIR}:
mkdir ${BUILDDIR}
ln -s ${MEM_INIT} ${BUILDDIR}

${BUILDDIR}/${TOP}.eblif: | ${BUILDDIR}
cd ${BUILDDIR} && synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} 2>&1 > /dev/null

${BUILDDIR}/${TOP}.net: ${BUILDDIR}/${TOP}.eblif
cd ${BUILDDIR} && pack -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null

${BUILDDIR}/${TOP}.place: ${BUILDDIR}/${TOP}.net
cd ${BUILDDIR} && place -e ${TOP}.eblif -d ${DEVICE} -p ${PCF} -n ${TOP}.net -P ${PARTNAME} -s ${SDC} 2>&1 > /dev/null

${BUILDDIR}/${TOP}.route: ${BUILDDIR}/${TOP}.place
cd ${BUILDDIR} && route -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null

${BUILDDIR}/${TOP}.fasm: ${BUILDDIR}/${TOP}.route
cd ${BUILDDIR} && write_fasm -e ${TOP}.eblif -d ${DEVICE}

${BUILDDIR}/${TOP}.bit: ${BUILDDIR}/${TOP}.fasm
cd ${BUILDDIR} && write_bitstream -d ${BITSTREAM_DEVICE} -f ${TOP}.fasm -p ${PARTNAME} -b ${TOP}.bit

clean:
rm -rf ${BUILDDIR}

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