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wishbone.bus: migrate to lib.wiring interfaces.
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Also, use Amaranth's lib.enum instead of standard enums.

Co-authored-by: Catherine <[email protected]>
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jfng and whitequark committed Sep 15, 2023
1 parent 7b52e93 commit c5e1e66
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Showing 3 changed files with 463 additions and 263 deletions.
8 changes: 4 additions & 4 deletions amaranth_soc/csr/wishbone.py
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
from amaranth.utils import log2_int

from . import Interface as CSRInterface
from ..wishbone import Interface as WishboneInterface
from .. import wishbone
from ..memory import MemoryMap


Expand All @@ -28,7 +28,7 @@ class WishboneCSRBridge(Elaboratable):
data_width : int
Wishbone bus data width. Optional. If ``None``, defaults to ``csr_bus.data_width``.
name : str
Window name. Optional.
Window name. Optional. See :class:`..memory.MemoryMap`.
Attributes
----------
Expand All @@ -46,11 +46,11 @@ def __init__(self, csr_bus, *, data_width=None, name=None):
data_width = csr_bus.data_width

self.csr_bus = csr_bus
self.wb_bus = WishboneInterface(
self.wb_bus = wishbone.Interface(
addr_width=max(0, csr_bus.addr_width - log2_int(data_width // csr_bus.data_width)),
data_width=data_width,
granularity=csr_bus.data_width,
name="wb")
path=("wb",))

wb_map = MemoryMap(addr_width=csr_bus.addr_width, data_width=csr_bus.data_width,
name=name)
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