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amanmogal authored Nov 29, 2024
1 parent 2d4f1b5 commit 4eb9da6
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2 changes: 2 additions & 0 deletions .vscode/settings.json
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{
}
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#ifndef DEBUG_CAPABILITIES_HPP
#define DEBUG_CAPABILITIES_HPP

#include <iostream>
#include <cstdint>
#include <arm_neon.h> // For SIMD support

class RegPrints {
public:
// Print general-purpose registers
static void print_gpr(const uint64_t& reg_value, const char* reg_name) {
std::cout << "Register " << reg_name << ": " << std::hex << reg_value << std::endl;
}

// Print vector registers (SIMD)
static void print_simd(const float32x4_t& reg_value, const char* reg_name) {
float values[4];
vst1q_f32(values, reg_value); // Store SIMD register into an array
std::cout << "SIMD Register " << reg_name << ": ["
<< values[0] << ", " << values[1] << ", "
<< values[2] << ", " << values[3] << "]" << std::endl;
}
};

#endif // DEBUG_CAPABILITIES_HPP
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Expand Up @@ -50,13 +50,18 @@ void jit_uni_eltwise_generic<isa>::generate() {
if (jep.use_runtime_ptrs) {
for (size_t i = 0; i < jep.inputs_number; i++) {
ldr(start_to_offsets, ptr(reg_const_params, static_cast<int32_t>(offsetof(node::jit_eltwise_call_args_ptrs, src_offsets) + i * sizeof(size_t))));
RegPrints::print_gpr(start_to_offsets.getIdx(), "start_to_offsets");
ldr(get_src_reg(i), ptr(reg_const_params, static_cast<int32_t>(offsetof(node::jit_eltwise_call_args_ptrs, src_ptr[0]) + i * sizeof(size_t))));
RegPrints::print_gpr(get_src_reg(i).getIdx(), "src_ptr");
XReg offset_reg = get_aux_gpr(0); // X_TMP_0;
XReg index_reg = get_aux_gpr(1); // X_TMP_1;
for (int j = 0; j < offset_count; j++) {
ldr(offset_reg, ptr(start_to_offsets, static_cast<int32_t>(j * sizeof(size_t))));
RegPrints::print_gpr(offset_reg.getIdx(), "offset_reg");
ldr(index_reg, ptr(reg_indexes, static_cast<int32_t>(j * sizeof(size_t))));
RegPrints::print_gpr(index_reg.getIdx(), "index_reg");
madd(get_src_reg(i), offset_reg, index_reg, get_src_reg(i));
RegPrints::print_gpr(get_src_reg(i).getIdx(), "effective_address");
}
}

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