#24 Improve timer scaling for first bit plane #37
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…architecture. Needs testing. Currently sets all to 12MHz target.
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Warning I did not run any tests on this code. My apologies.
The code is a simple fix for making sure the first bit plane has enough time to shift out completely. It still limits the performance to 250Hz framerate. However for larger panels this ended up causing a problem potentially.
A macro was added which defines the max LED shift register clock. This effectively drives everything for these panels, so this is a nice clean number to base certain things on. The issue however is this derived from software so it will be dependent on processor speed. It does account for any differences in the compiler or processor architecture.
A faster processor will be capable of higher bandwidth. Future work is figuring out the limits of each architecture. Also scaling this performance against the processor clock. This was mentioned in #11.