Simple Floating Point Unit

A Floating-Point Arithmetic Unit implemented in SystemVerilog

Arithmetic Unit Diagrams

The Sign Unit implements the following logic:

Name		Name	Last commit message	Last commit date
Latest commit History 33 Commits
Count_Leading_Zeros		Count_Leading_Zeros
Images		Images
ModelSim_Waves		ModelSim_Waves
.gitignore		.gitignore
README.md		README.md
float_adder_double.sv		float_adder_double.sv
float_adder_single.sv		float_adder_single.sv
float_divider.sv		float_divider.sv
float_multiplier.sv		float_multiplier.sv
fpu_double.sv		fpu_double.sv
fpu_single.sv		fpu_single.sv
mux.sv		mux.sv
opcodes.svh		opcodes.svh
runlab.do		runlab.do