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Draft Extension: ZiCond #97

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Draft Extension: ZiCond #97

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@a4lg a4lg commented Nov 30, 2022

@a4lg a4lg added the enhancement New feature or request label Nov 30, 2022
@a4lg a4lg force-pushed the riscv-zicond branch 3 times, most recently from f6ef441 to bc6db8b Compare December 2, 2022 03:27
@a4lg a4lg force-pushed the riscv-zicond branch 4 times, most recently from f45f3cc to 2ec05e2 Compare December 11, 2022 06:32
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@a4lg
UNRATIFIED RISC-V: Add 'ZiCond' extension
2326b12 
[DO NOT MERGE]
Until 'ZiCond' extension is frozen/ratified and final version number is
determined, this patch should not be merged upstream.  This commit uses
version 1.0 as in the documentation.

This commit adds support for the latest draft of RISC-V Integer Conditional
(ZiCond) extension consisting of 2 new instructions.

This is based on the early draft of 'ZiCond' extension on GitHub:
<riscvarchive/riscv-zicond@e05301d>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_supported_std_z_ext): Add 'ZiCond'.
	(riscv_multi_subset_supports): Support new instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zicond.s: New test for 'ZiCond'.
	* testsuite/gas/riscv/zicond.d: Likewise.
	* testsuite/gas/riscv/zicond-noarch.d: New test for
	architecture failure.
	* testsuite/gas/riscv/zicond-noarch.l: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_CZERO_EQZ, MASK_CZERO_EQZ,
	MATCH_CZERO_NEZ, MASK_CZERO_NEZ): New.
	* opcode/riscv.h (enum riscv_insn_class): Add new instruction
	class INSN_CLASS_ZICOND.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add new instructions from the
	'ZiCond' extension.
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a4lg commented Jul 24, 2023

As the support for this extension is upstreamed by Philipp Tomsich, this branch is no longer necessary.

@a4lg a4lg closed this Jul 24, 2023
@a4lg a4lg deleted the riscv-zicond branch July 24, 2023 07:15
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