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Disassembler: Core Optimization 1-1 (Hash table and Caching) #88

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Disassembler: Core Optimization 1-1 (Hash table and Caching) #88

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@a4lg a4lg commented Nov 17, 2022

@a4lg a4lg force-pushed the riscv-dis-opt1-req-reorganize branch from 6c23d80 to 992c0f5 Compare November 18, 2022 00:12
@a4lg a4lg force-pushed the riscv-dis-opt1-1-hashtable-and-caching branch 2 times, most recently from 444fbaa to b83e54a Compare November 18, 2022 04:58
@a4lg a4lg force-pushed the riscv-dis-opt1-req-reorganize branch from 76a3a4e to d312be0 Compare November 19, 2022 02:38
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@a4lg a4lg force-pushed the riscv-dis-opt1-req-reorganize branch from 68d5006 to 452c070 Compare November 19, 2022 11:57
@a4lg a4lg force-pushed the riscv-dis-opt1-1-hashtable-and-caching branch from f99c8ca to 297008a Compare November 19, 2022 11:57
@a4lg a4lg added the enhancement New feature or request label Nov 19, 2022
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a4lg added 3 commits October 19, 2023 06:58
@a4lg
RISC-V: Use faster hash table on disassembling
a497437 
This commit improves performance on disassembling RISC-V code.
It replaces riscv_hash (in opcodes/riscv-dis.c) with much faster data
structure: a sorted and partitioned hash table.

This is a technique actually used on SPARC architecture
(opcodes/sparc-dis.c) and the author simplified the algorithm even further.
Unlike SPARC, RISC-V's hashed opcode table is not a table to linked lists,
it's just a table, pointing "start" elements in the sorted opcode list
(per hash code) and a global tail.

It is expected to have 20-40% performance improvements when disassembling
linked RISC-V ELF programs using objdump.  That is a significant improvement
and pretty nice for such a small modification
(with about 12KB heap memory allocation on 64-bit environment).

This is not the end.  This structure significantly improves plain binary
file handling (on objdump, "objdump -b binary -m riscv:rv[32|64] -D $FILE").

The author tested on various binary files including random one and big
vmlinux images and confirmed significant performance improvements (>70%
on many cases).  This is partially due to the fact that, disassembling about
one quarter of invalid "instruction" words required iterating over one
thousand opcode entries (348 or more being vector instructions with OP-V,
that can be easily skipped with this new data structure).  Another reason
for this significance is it doesn't have various ELF overhead.

opcodes/ChangeLog:

	* riscv-dis.c (init_riscv_dis_state_for_arch_and_options): Build
	the hash table on the first run.
	(OP_HASH_LEN): Move from riscv_disassemble_insn.
	(OP_HASH_IDX): Move from riscv_disassemble_insn and mask by
	OP_MASK_OP2 == 0x03 for only real 16-bit instructions.
	(riscv_hash): New sorted and partitioned hash table.
	(riscv_opcodes_sorted): New sorted opcode table.
	(compare_opcodes): New function to compare RISC-V opcode entries.
	(build_riscv_opcodes_hash_table): New function to build faster
	hash table to disassemble.
	(riscv_disassemble_insn): Use sorted and partitioned hash table.
@a4lg
RISC-V: Fallback on faster hash table
6b3d067 
Although it does not have a problem on current GNU Binutils implementation,
if the custom vendor implements an instruction which spans across multiple
major opcodes (e.g. uses both CUSTOM_0 and CUSTOM_1 in a *single* custom
instruction), the original assumption of the sorted hash table breaks.

In this case, this commit enables the fallback mode to disable all
optimizations except filtering macros out.

Note that, if a such instruction (that disables this disassembler
optimization) is upstreamed to Binutils, a separate solution will be
required to avoid major performance degradation when such instruction is
not used.  The intent of this commit is to make a room for custom vendors
to implement such instructions in *their* tree without causing
disassembler problems.

opcodes/ChangeLog:

	* riscv-dis.c (is_riscv_hash_fallback) New.
	(build_riscv_opcodes_hash_table): If an instruction spans across
	multiple major opcodes, enable fallback mode and disable sorting.
	(riscv_disassemble_insn): If the fallback mode is enabled, scan
	through all instructions instead of scanning only instruction
	entries matching the hash value.
@a4lg
RISC-V: Cache instruction support
496ea7d 
Calling riscv_subset_supports repeatedly harms the performance in a
measurable way (about 3-13% in total on the most cases).

As a simple solution, this commit now caches instruction class support
(whether specific instruction class is supported) as a signed char array.

It is expected to have 5-7% performance improvements when disassembling
linked RISC-V ELF programs using objdump but this is particularly effective
with programs with many CSR instructions (up to ~42% on the author's PC).

include/ChangeLog:

	* opcode/riscv.h (enum riscv_insn_class): Add NUM_INSN_CLASSES.

opcodes/ChangeLog:

	* riscv-dis.c (riscv_insn_support_cache) New.
	(init_riscv_dis_state_for_arch): Clear the instruction support
	cache.  (riscv_disassemble_insn): Cache the instruction support.
@a4lg a4lg force-pushed the riscv-dis-opt1-1-hashtable-and-caching branch from 30b8505 to 496ea7d Compare October 19, 2023 07:01
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